请问在IOSERDES2中行数据是在DDR模式下输出的吗？

这是我尝试回答您问题的第3稿。
在初稿中。
我无知。
在第二稿中，我改编了SDR而不是DDR。
在第3稿中，我将尝试使用DDR模式直接回答您的问题。
1.在serdes_1_to_n_clk_ddr_s8_diff.v / vhd我修改了BUFIO2
除以3得到80MHz信号然后我可以用于gclk
（即并行clk）用于SERDES。
我不确定我是否正确
这样做。
我应该使用Divide by 6获得40MHz还是3才能获得80MHz？
UG382（v1.4）图1-15和XAPP1064.pdf（v1.1，第4页，最后一段）看起来很清楚。
您需要设置BUFIO2参数DIVIDE = 6，并且因为您还设置DOUBLER = TRUE，结果将是DIVCLK（和serdesstrobe）输出频率为80MHz。
这应该导致6位并行输出字。
2.在IOSERDES2中，并行数据是在DDR模式下输出的吗？
（与问题1有关）
从80MHz时钟的角度来看，答案是否定的，ISERDES2模块具有单个“字速率”或结构时钟，用于注册反序列化数据。
该时钟是来自（主）BUFIO2的80MHz DIVCLK（ISERDES2处于“RETIMED”模式）或serdesstrobe（处于“NETWORKING + PIPELINED”模式）。
从40MHz的角度来看（见下面的答案＃3），答案是肯定的：ISERDES2 6位输出是DDR（相对于40MHz时钟）。
与在DDR模式下运行的ISERDES2相比，UG381，UG382和xAPP1064.pdf中的信息严重不足。
例如，UG382图1-15 BUFIO2（x2）驱动ISERDES2工作在DDR模式下的图：CLKDIV，CLK0，CLK1端口清楚标注;
它们在UG381中被清楚标明（表3-1）;
但这些相同的端口完全缺失（并且缺少对应的线索）到UG381图3-1（ISERDES2块的框图）;
XAPP1064.pdf中缺少“连接”（图6和相关文本）。
缺少的信息足够严重（并且足够有用），值得一个webcase来解决这个问题。
如果您不想打开一个，请告诉我，我会打开一个（但不要期望立即回复技术细节）。
3.为12生成40Mhz时钟的最佳位置在哪里
位拓宽功能？
我可以从ADC访问帧时钟 
运行在40MHz或者我可以在gtx时钟上使用DCM（命名为
示例中的rx_bufg_x1）
第二个BUFIO2在DOUBLER = FALSE模式下运行。
其未使用的DIVCLK输出为40MHz。
您可以使用此输出（使用BUFG缓冲它）用于一般结构使用。
通过一些实验，您可以毫不费力地将6位ISERDES2输出字视为DDDR数据（相对于40MHz结构时钟）。
使用40MHz时钟的两个边沿来解复用数据并将12位字对齐到单个时钟边沿应该是直截了当的。
没有足够的信息来确定如何从ADC帧时钟完成字帧。
在将脉冲和数据从一个时钟域与另一个时钟域（包括帧时钟）对齐时，不要忘记使用亚稳避免措施。
希望这可以帮助...
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
在原帖中查看解决方案



以下为原文

This is my 3rd draft attempt to answer your questions.  In the first draft. I pled ignorance.  In the 2nd draft I proselytised SDR instead of DDR.  In this 3rd draft, I'll try to straight-on answer your questions using DDR mode.

1. In serdes_1_to_n_clk_ddr_s8_diff.v/vhd I modified the BUFIO2 divide to be 3 to get an 80MHz signal that I can then use for the gclk (i.e. parallel clk) for the SERDES. I'm not sure if I am correct in doing that. Should I use Divide by 6 to get 40MHz or 3 to get 80MHz?

UG382 (v1.4) Figure 1-15 and XAPP1064.pdf (v1.1, page 4, last paragraph) seem pretty clear.  You need to set the BUFIO2 parameter DIVIDE=6, and because you are also setting DOUBLER=TRUE the result will be a DIVCLK (and serdesstrobe) output frequency of 80MHz.  This should result in 6-bit parallel output words.

2. In the IOSERDES2 is the parallel data being clocked out in DDR mode? (Related to Question 1)

From an 80MHz clock perspective, the answer is NO, the ISERDES2 block has a single "word rate" or fabric clock for registering the deserialised data.  This clock is the 80MHz DIVCLK (ISERDES2 in "RETIMED" mode) or serdesstrobe (in "NETWORKING + PIPELINED" mode) from the (primary) BUFIO2.  From a 40MHz perspective (see answer #3 below), the answer is YES: the ISERDES2 6-bit output is DDR (with respect to 40MHz clock).
 
Information in UG381, UG382, and xAPP1064.pdf is woefully inadequate with respect to ISERDES2 operating in DDR mode.   For example, UG382 Figure 1-15 diagram of BUFIO2 (x2) driving ISERDES2 operating in DDR mode:  the CLKDIV, CLK0, CLK1 ports are clearly labeled; they are labeled clearly in UG381 (Table 3-1); but these same ports are completely missing (and absent clues for correspondence) to UG381 Figure 3-1 (the block diagram of the ISERDES2 block); and the missing "connection" is absent in XAPP1064.pdf (Figure 6 and related text).
 
The missing information is serious enough (and useful enough) to deserve a webcase to address this.  If you don't want to open one, let me know and I'll open one (but don't expect an immediate response on the technical details).

3. Where is the best place to generate the 40Mhz clock for the 12 bits widening function? I have access to a frame clock from the ADC that is running at 40MHz or I can use a DCM on the gtx clock (named rx_bufg_x1 in the example)

The second BUFIO2 is operating in DOUBLER=FALSE mode.  Its unused DIVCLK output will be 40MHz.  You can use this output (buffer it with a BUFG) for general fabric use.  With a little bit of experimentation, you should have no problem treating the 6-bit ISERDES2 output words as DDDR data (with respect to the 40MHz fabric clock).  Using both edges of the 40MHz clock to demux the data and align the 12-bit words to a single clock edge should be straightforward.
 
There isn't enough information to determine how word framing is accomplished from the ADC frame clock.  Don't forget to use metastable avoidance measures when aligning pulses and data from one clock domain to another (including the framing clock).
 
Hope this helps...
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

这是我尝试回答您问题的第3稿。
在初稿中。
我无知。
在第二稿中，我改编了SDR而不是DDR。
在第3稿中，我将尝试使用DDR模式直接回答您的问题。
1.在serdes_1_to_n_clk_ddr_s8_diff.v / vhd我修改了BUFIO2
除以3得到80MHz信号然后我可以用于gclk
（即并行clk）用于SERDES。
我不确定我是否正确
这样做。
我应该使用Divide by 6获得40MHz还是3才能获得80MHz？
UG382（v1.4）图1-15和XAPP1064.pdf（v1.1，第4页，最后一段）看起来很清楚。
您需要设置BUFIO2参数DIVIDE = 6，并且因为您还设置DOUBLER = TRUE，结果将是DIVCLK（和serdesstrobe）输出频率为80MHz。
这应该导致6位并行输出字。
2.在IOSERDES2中，并行数据是在DDR模式下输出的吗？
（与问题1有关）
从80MHz时钟的角度来看，答案是否定的，ISERDES2模块具有单个“字速率”或结构时钟，用于注册反序列化数据。
该时钟是来自（主）BUFIO2的80MHz DIVCLK（ISERDES2处于“RETIMED”模式）或serdesstrobe（处于“NETWORKING + PIPELINED”模式）。
从40MHz的角度来看（见下面的答案＃3），答案是肯定的：ISERDES2 6位输出是DDR（相对于40MHz时钟）。
与在DDR模式下运行的ISERDES2相比，UG381，UG382和xAPP1064.pdf中的信息严重不足。
例如，UG382图1-15 BUFIO2（x2）驱动ISERDES2工作在DDR模式下的图：CLKDIV，CLK0，CLK1端口清楚标注;
它们在UG381中被清楚标明（表3-1）;
但这些相同的端口完全缺失（并且缺少对应的线索）到UG381图3-1（ISERDES2块的框图）;
XAPP1064.pdf中缺少“连接”（图6和相关文本）。
缺少的信息足够严重（并且足够有用），值得一个webcase来解决这个问题。
如果您不想打开一个，请告诉我，我会打开一个（但不要期望立即回复技术细节）。
3.为12生成40Mhz时钟的最佳位置在哪里
位拓宽功能？
我可以从ADC访问帧时钟 
运行在40MHz或者我可以在gtx时钟上使用DCM（命名为
示例中的rx_bufg_x1）
第二个BUFIO2在DOUBLER = FALSE模式下运行。
其未使用的DIVCLK输出为40MHz。
您可以使用此输出（使用BUFG缓冲它）用于一般结构使用。
通过一些实验，您可以毫不费力地将6位ISERDES2输出字视为DDDR数据（相对于40MHz结构时钟）。
使用40MHz时钟的两个边沿来解复用数据并将12位字对齐到单个时钟边沿应该是直截了当的。
没有足够的信息来确定如何从ADC帧时钟完成字帧。
在将脉冲和数据从一个时钟域与另一个时钟域（包括帧时钟）对齐时，不要忘记使用亚稳避免措施。
希望这可以帮助...
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

This is my 3rd draft attempt to answer your questions.  In the first draft. I pled ignorance.  In the 2nd draft I proselytised SDR instead of DDR.  In this 3rd draft, I'll try to straight-on answer your questions using DDR mode.

1. In serdes_1_to_n_clk_ddr_s8_diff.v/vhd I modified the BUFIO2 divide to be 3 to get an 80MHz signal that I can then use for the gclk (i.e. parallel clk) for the SERDES. I'm not sure if I am correct in doing that. Should I use Divide by 6 to get 40MHz or 3 to get 80MHz?

UG382 (v1.4) Figure 1-15 and XAPP1064.pdf (v1.1, page 4, last paragraph) seem pretty clear.  You need to set the BUFIO2 parameter DIVIDE=6, and because you are also setting DOUBLER=TRUE the result will be a DIVCLK (and serdesstrobe) output frequency of 80MHz.  This should result in 6-bit parallel output words.

2. In the IOSERDES2 is the parallel data being clocked out in DDR mode? (Related to Question 1)

From an 80MHz clock perspective, the answer is NO, the ISERDES2 block has a single "word rate" or fabric clock for registering the deserialised data.  This clock is the 80MHz DIVCLK (ISERDES2 in "RETIMED" mode) or serdesstrobe (in "NETWORKING + PIPELINED" mode) from the (primary) BUFIO2.  From a 40MHz perspective (see answer #3 below), the answer is YES: the ISERDES2 6-bit output is DDR (with respect to 40MHz clock).
 
Information in UG381, UG382, and xAPP1064.pdf is woefully inadequate with respect to ISERDES2 operating in DDR mode.   For example, UG382 Figure 1-15 diagram of BUFIO2 (x2) driving ISERDES2 operating in DDR mode:  the CLKDIV, CLK0, CLK1 ports are clearly labeled; they are labeled clearly in UG381 (Table 3-1); but these same ports are completely missing (and absent clues for correspondence) to UG381 Figure 3-1 (the block diagram of the ISERDES2 block); and the missing "connection" is absent in XAPP1064.pdf (Figure 6 and related text).
 
The missing information is serious enough (and useful enough) to deserve a webcase to address this.  If you don't want to open one, let me know and I'll open one (but don't expect an immediate response on the technical details).

3. Where is the best place to generate the 40Mhz clock for the 12 bits widening function? I have access to a frame clock from the ADC that is running at 40MHz or I can use a DCM on the gtx clock (named rx_bufg_x1 in the example)

The second BUFIO2 is operating in DOUBLER=FALSE mode.  Its unused DIVCLK output will be 40MHz.  You can use this output (buffer it with a BUFG) for general fabric use.  With a little bit of experimentation, you should have no problem treating the 6-bit ISERDES2 output words as DDDR data (with respect to the 40MHz fabric clock).  Using both edges of the 40MHz clock to demux the data and align the 12-bit words to a single clock edge should be straightforward.
 
There isn't enough information to determine how word framing is accomplished from the ADC frame clock.  Don't forget to use metastable avoidance measures when aligning pulses and data from one clock domain to another (including the framing clock).
 
Hope this helps...
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

作为一个有点相关的说明，我打开了一个webcase，寻求澄清DDR模式下的ISERDES2操作。
webcase提交的文本如下：
在DDR模式下使用ISERDES2时，如何使用CLK0，CLK1和CLKDIV输入？
ISERDES2输出到CLKDIV的时序关系是什么？为什么ISERDES2的CLK0和CLK1输入端口不包含在ISERDES2框图UG381中？图3-1？在UG615 v12.3第145-147页中，CLK0和CLK1输入的描述说
这些输入是可逆的。
ISERDES2的属性列表不包括CLK0或CLK1输入的“反转”属性。
相同的评论适用于UG381 v1.3第71-73页 
DDR模式操作，为什么需要2个BUFIO？
为什么不是一个BUFIO
IOCLK输出连接到ISERDES2 CLK0和CLK1输入，带CLK1
输入倒置？
如何选择反相CLK0或CLK1输入
ISERDES2？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

As a somewhat related note, I've opened a webcase seeking clarification of ISERDES2 operation in DDR mode.  Text of the webcase submission as follows:

When using ISERDES2 in DDR mode, how are the CLK0, CLK1, and CLKDIV inputs used?  What is the timing relationship of ISERDES2 output to CLKDIV?

Why are the CLK0 and CLK1 input ports to ISERDES2 not included in ISERDES2 block diagram UG381 Fig 3-1?

In UG615 v12.3 page 145-147, description of CLK0 and CLK1 inputs says these inputs are invertible.  The attribute list for ISERDES2 does not include the "invert" attribute for CLK0 or CLK1 inputs.  Same comments apply to UG381 v1.3 pages 71-73.

For DDR mode operation, why are 2 BUFIOs needed?  Why not a single BUFIO with IOCLK output connected to ISERDES2 CLK0 and CLK1 input, with CLK1 input inverted?  How do you select inverted CLK0 or CLK1 inputs to ISERDES2?

 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨鲍勃，
在DDR模式下使用ISERDES2时，如何使用CLK0，CLK1和CLKDIV输入？
CLK0是图3-1中所示的IO clk。
CLK1也是IOCLK，但该图基本上是SDR版本。
我相信他们用它来简化事情。
他们主要试图说明模式之间的差异 - 重新定时，网络线路和网络。
ISERDES2输出到CLKDIV的时序关系是什么？
为什么ISERDES2的CLK0和CLK1输入端口不包含在ISERDES2框图UG381中？图3-1？
CLKDIV是结构时钟，用于将ISERDES2的输出计时到结构中。
因此，基本上ISERDES2的最后一个时钟与CLKDIV的相位相同.3-1中显示的全局时钟应为CLKDIV。
我建议将它们重命名给作者。
在UG615 v12.3第145-147页中，CLK0和CLK1输入的描述表明这些输入是可逆的。
ISERDES2的属性列表不包括CLK0或CLK1输入的“反转”属性。
相同的评论适用于UG381 v1.3第71-73页。
我相信这是指具有反转信号能力的硬件。可以在HDL中完成反演。
（它们并不意味着动态反转。）我在XAP1064中没有找到这样的例子，因此它不是常态。
我会跟进作者。
对于DDR模式操作，为什么需要2个BUFIO？
为什么单个BUFIO的IOCLK输出连接到ISERDES2 CLK0和CLK1输入，CLK1输入反转？
对此没有快速回答。
[R
--------------------------------------------------
--------------------------不要忘记回复，不要接受作为解决方案-----------
--------------------------------------------------
---------------



以下为原文

Hi Bob,
 
When using ISERDES2 in DDR mode, how are the CLK0, CLK1, and CLKDIV inputs used?
 
CLK0 is the IO clk shown in diagram 3-1.  CLK1 is also an IOCLK but the diagram is bascially the SDR version.  I believe they use this to simplify things.  They are mainly trying to illustrate the differences between the modes - retimed, networking_piplined and networking.
 
What is the timing relationship of ISERDES2 output to CLKDIV?  Why are the CLK0 and CLK1 input ports to ISERDES2 not included in ISERDES2 block diagram UG381 Fig 3-1?


CLKDIV is the fabric clock that is designed to clock the output of the ISERDES2 into the fabric.  So basically the last clock out of the ISERDES2 is the same phase as CLKDIV.  The global clock shown in 3-1 should be CLKDIV.  I will suggest renaming them to the author.
 

In UG615 v12.3 page 145-147, description of CLK0 and CLK1 inputs says these inputs are invertible. The attribute list for ISERDES2 does not include the "invert" attribute for CLK0 or CLK1 inputs. Same comments apply to UG381 v1.3 pages 71-73.


I beleive this refers to the hardware having the ability to invert the signal.  The inversion could be done in the HDL. ( They don't mean dynamic inversion. )   I found no examples of this in XAP1064 so it is not the norm.  I will follow up with the author.
 


For DDR mode operation, why are 2 BUFIOs needed? Why not a single BUFIO with IOCLK output connected to ISERDES2 CLK0 and CLK1 input, with CLK1 input inverted?
 

Don't have a quick answer on this one.
 
R



 
 
----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------

@roym
为什么gdowg发布了这个帖子是完全可以理解的。
ISERDES2的DDR模式在某种程度上“未被记录”。
虽然gdowg现在需要具体的详细答案，但那些可能跟随他的脚步的人将受益于填写不完整的描述，定义表和图表的文档更新。
webcase是＃855580。如果你有时间'采用'这种情况，我们可以很快地一起鞭打它。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
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提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

@roym
It's completely understandable why  gdowg posted this thread.  DDR mode for ISERDES2 is somewhat "under-documented".
 
While gdowg is in need of the specific detailed answers now, those who might follow in his footsteps would benefit from the doc updates which fill in the incomplete set of descriptions, definition tables, and diagrams.
 
The webcase is # 855580.  If you have the time to 'adopt' this case, we can whip through it together rather quickly.
 
-- Bob Elkind
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好的，我将在webcase上工作。
我可以告诉你，从长远来看，针对此计划的应用笔记是有计划的。
干杯，
罗伊
--------------------------------------------------
--------------------------不要忘记回复，不要接受作为解决方案-----------
--------------------------------------------------
---------------



以下为原文

OK, I'll be working on the webcase.
 
I can tell you that in the long run an application note aimed at this is planned.
 
Cheers,
Roy
----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------

我可以告诉你，从长远来看，针对此计划的应用笔记是有计划的。
这将是Xilinx doc set的一个非常有用的补充。
我确信这是一项重大任务，但值得付出努力。
谢谢你的帮助，罗伊。
- 鲍勃
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

I can tell you that in the long run an application note aimed at this is planned.

This will be a very useful addition to Xilinx doc set.  I'm sure this is a significant undertaking, but well worth the effort.
 
Thanks for your help, Roy.
 
- Bob
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嗨鲍勃，非常感谢您的解释！
实际上，这是我第一次发布这个主题。
现在看起来很明显，但起初我觉得它真的很混乱。
你的解释为我清除了很多不确定因素。
如果我设置DIVIDE = 6（对于240MHz位时钟），结果将是40MHz，我一直挂断了这个事实。我不知道我是怎么完全错过了BUFIO2_2CLK（bufio2_2clk_inst）运行的事实
USE_DOUBLER = TRUE模式下的BUFIO2。
现在，设置DIVIDE = 6并且仍能够获得80MHz时钟是可以的。
--------------------------------------------------
--------------------------------------------------
--------------------------
摘自UG382 ... BUFIO2_2CLK（图1-33）与BUFIO2（USE_DOUBLER = TRUE）具有几乎相同的功能，除了它需要两个单端时钟或差分对（IBUFDS_DIFF_OUT的输出）。
表1-20列出了BUFIO2_2CLK端口。
表1-21列出了属性。
--------------------------------------------------
--------------------------------------------------
--------------------------
它比以前工作得更好，但我仍然有1或2个坏包
在ChipScope Pro的512个样本窗口内。
我正在使用具有80MHz wr时钟和40MHz rd时钟的FIFO。
同样出于测试目的，我正在使用手册
通过ChipScope Pro中的VIO模块进行bitlip控制。
你在下面的评论中是什么意思？
您是在谈论lvds数据和位时钟之间DDR的OFFSET时序约束吗？
没有足够的信息来确定单词框架是如何形成的
从ADC帧时钟完成。
别忘了使用亚稳态
在对齐来自一个时钟域的脉冲和数据时的避免措施
到另一个（包括框架时钟）。
谢谢你！



以下为原文

Hi Bob,
Thanks so much for your explaination!! Actually, this is the first time I posted on this topic. Now it seems pretty obvious, but it seemed really confusing to me at first. Your explaination cleared up a lot of uncertainty for me. I kept getting hung up on the fact that if I would have set DIVIDE=6 (for a 240MHz bit clock) that the result would be 40MHz.
I don't know how I totally missed the fact that the BUFIO2_2CLK (bufio2_2clk_inst) operates like a BUFIO2 in USE_DOUBLER=TRUE mode.
 
Now, it makes sense how it's okay to set DIVIDE=6 and still be able to get out an 80MHz clock.


------------------------------------------------------------------------------------------------------------------------------
Excerpt from UG382...
The BUFIO2_2CLK (Figure 1-33) has almost the same functionality as the BUFIO2
(USE_DOUBLER = TRUE) except it takes two single-ended clocks or a differential pair
(output from IBUFDS_DIFF_OUT). Table 1-20 lists the BUFIO2_2CLK ports. Table 1-21
lists the attributes.
------------------------------------------------------------------------------------------------------------------------------
 
It's working better than before, but I still have 1 or 2 bad packets within a 512 sample window in ChipScope Pro. I'm using a FIFO with 80MHz wr clock and 40MHz rd clock. Also for testing purposes I'm using a manual bitslip control through a VIO block in ChipScope Pro.
 
What did you mean by the comment below? Are you speaking about the OFFSET timing constraints for DDR between the lvds data and the bit clock?
 
There isn't enough information to determine how word framing is accomplished from the ADC frame clock.  Don't forget to use metastable avoidance measures when aligning pulses and data from one clock domain to another (including the framing clock).


Thanks agian!!

 

罗伊，
感谢您的信息。



以下为原文

Roy,
Thank you for the information.

注意：我在这篇文章中撤回了我的一些结论。
一个更完整的解释是在同一个帖子的后续帖子中有几个帖子。
- 鲍勃埃尔金德
它比以前工作得更好，但我仍然有1或2个坏包
在ChipScope Pro的512个样本窗口内。
...还用于测试目的我正在使用
手册
通过ChipScope Pro中的VIO模块进行bitlip控制。
Xilinx已经选择保持BITSLIP功能的内部工作机密（是的，我已经在这个主题上提交了一两个webcase），并且当前的一组文档没有提供足够的信息来满足我。
所以我选择不使用BITSLIP功能，而是在结构中实现字框架。
我记得（也许是错误的）读取BITSLIP和SERDESSTROBE（也称为IOCE）功能是互斥的。
我无法找到我记得读到这里的地方，所以要怀疑地看一下这个警告。
在DDR模式下，您可能正在使用SERDESSTROBE功能（参见图1-15中的UG382）。
您可能希望自己向Xilinx确认可以同时使用BITSLIP和SERDESSTROBE。
[更新：我完整地撤回这一段 - 鲍勃]
当我盯着UG381图3-1足够长时，我确信当与SERDESSTROBE / IOCE一起使用时，BITSLIP不会做任何事情（除了可能搞砸了）。
但话说回来，也许UG381图3-1应该被视为一个过于简化的图表。
[更新：阅读我的后续帖子，了解为什么我的结论发生了变化 - 鲍勃]
在你无限的业余时间里，你可能想要阅读roym和我之间关于BITSLIP主题的这种交流。
不幸的是，关于Spartan 6 ISERDES的文档很复杂。
缺少细节（重要的东西！），过于简化的图纸，缺少图纸（例如DDR模式信号定时），以及命名和标签的不一致。
更令人困惑的是，Xilinx支持（取决于您绘制的人）难以浏览文档并整理出ISERDES2细节。
在开发过程中，ISERDES2用户指南（或应用笔记，正如Roy所描述的那样）有望在一个文档中整合所有必要的信息，清理不一致的内容，并填写丢失的拼图。
re：framing，你写道：
我可以从运行频率为40MHz的ADC访问帧时钟。
我跟进了：
别忘了使用亚稳态
在对齐来自一个时钟域的脉冲和数据时的避免措施
到另一个（包括框架时钟）。
考虑到设计中运行的各种时钟信号，不要忽视无意中时钟域交叉的可能性。
如果你不知道一个时钟信号和另一个时钟信号之间的相位关系，你有理由担心。
注意：Roy（roym）是关于ISERDES2主题的最知识渊博的人之一。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

NOTE:  I retract some of my conclusions in this posting.  A more complete explanation is in a followup post several posts down from this one, in this same thread.  - Bob Elkind

It's working better than before, but I still have 1 or 2 bad packets within a 512 sample window in ChipScope Pro. ... Also for testing purposes I'm using a manual bitslip control through a VIO block in ChipScope Pro.

Xilinx has chosen to keep the BITSLIP function's inner workings secret (yes, I've filed a webcase or two on the subject), and the current set of docs do not provide enough information to satisfy me.  So I've chosen to not use the BITSLIP feature, and I've implement word framing in the fabric instead.
 
I remember (perhaps incorrectly) reading that BITSLIP and SERDESSTROBE (also called IOCE) functions were mutually exclusive.  I cannot find where I remember reading this, so view this warning with some suspicion.  In DDR mode, you are probably using the SERDESSTROBE function (see UG382 figure 1-15).  You may wish to confirm on your own with Xilinx that BITSLIP and SERDESSTROBE may be used concurrently.  [UPDATE: I retract this paragraph in its entirety - Bob]
 
When I stared at UG381 Figure 3-1 long enough, I was convinced that BITSLIP doesn't do a darn thing (except possibly screw things up) when used with SERDESSTROBE/IOCE.  But then again, perhaps UG381 Fig 3-1 should be taken as an oversimplified diagram. [UPDATE: read my followup post on why my conclusions have changed - Bob]
 
In your infinite spare time, you may want to read this exchange between roym and me on the subject of BITSLIP.
 
Unfortunately, the documentation on Spartan 6 ISERDES is a mixed bag.  There are missing details (on important stuff!), oversimplified drawings, missing drawings (e.g. DDR mode signal timing), and inconsistencies in naming and labeling.  Adding to the confusion is that Xilinx support (depending on who you draw) has difficulty wading through the docs and sorting out ISERDES2 details as well.   The ISERDES2 user guide (or app note, as Roy characterised it) in development will hopefully consolidate all the necessary information in one doc, clean up the inconsistencies, and fill in the missing puzzle pieces.
 
re: framing, you wrote:

I have access to a frame clock from the ADC that is running at 40MHz.

I followed up with:

Don't forget to use metastable avoidance measures when aligning pulses and data from one clock domain to another (including the framing clock).

Don't overlook the possibilities of inadvertent clock domain crossings, given the various clock signals running around in your design.  If you don't know the phase relationship between one clock signal and another, you have reason to be concerned.
 
NOTE:  Roy (roym) is one of the most knowledgeable folks on the subject of ISERDES2.

 
-- Bob Elkind

 
 
 
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