如何实现OSERDES在DDR模式下以125MHz时钟运行？

设备内的任何时钟都是SDR。
所以你的50MHz示例也由OSERDES从SDR模式转换为DDR。
您可以使用相同的方法在DDR模式下通过OSERDES转发DCM生成的125MHz时钟。
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----------------------------别忘了回复，给予kudo并接受为解决方案---------
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以下为原文

Any clock inside the device is SDR. So your 50MHz example also is converted from SDR mode to DDR by OSERDES.

You could use the same method to forward 125MHz clock generated by DCM through OSERDES in DDR mode.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
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嗨Venkata，
感谢您的回复，
设备内的任何时钟都是SDR。
所以你的50MHz示例也由OSERDES从SDR模式转换为DDR。 
我知道即将到来的50 MHz是SDR，它会在OSERDES中转换为DDR
您可以使用相同的方法在DDR模式下通过OSERDES转发DCM生成的125MHz时钟。 
当我使用相同的方法转发125 MHz时钟时，我从MAP获得错误
错误：位置：1136  - 此设计包含一个全局缓冲区实例， 
，驾驶网，即驾驶 
以下（前30个）非时钟加载引脚。    
由于受到限制，这不是Spartan-6中推荐的设计实践 
可能导致过度延迟，倾斜或不可路由的全局路由 
的情况。
建议仅使用BUFG资源来驱动时钟 
负载。
如果您希望覆盖此建议，可以使用 
.ucf文件中的CLOCK_DEDICATED_ROUTE约束（如下所示）降级 
此消息发送到警告并允许您的设计继续。 
我的50 MHz信号通过两个BUFIO2，为OSERDES2，divclk和OSERDES选通信号产生信号。
如何使用DCM生成125MHz时钟信号并通过两个BUFIO2来解决此错误
谢谢
穆斯塔法



以下为原文

Hi Venkata,
Thanks for your reply,
 

• Any clock inside the device is SDR. So your 50MHz example also is converted from SDR mode to DDR by OSERDES. 
  

     I know that 50 MHz that coming is SDR and it gets converted in OSERDES to DDR
 

• You could use the same method to forward 125MHz clock generated by DCM through OSERDES in DDR mode.
  

     When I use the same method to forward the 125 MHz clock I get an error from MAP

ERROR:Place:1136 - This design contains a global buffer instance,   , driving the net, , that is driving   the following (first 30) non-clock load pins.   < PIN: OSRDS_ClkGen_inst/BUFIO2_noDoubler_inst.I; >   < PIN: OSRDS_ClkGen_inst/BUFIO2_doubler_inst.I; >   < PIN: OSRDS_ClkGen_inst/BUFIO2_doubler_inst.IB; >   This is not a recommended design practice in Spartan-6 due to limitations in   the global routing that may cause excessive delay, skew or unroutable   situations.  It is recommended to only use a BUFG resource to drive clock   loads. If you wish to override this recommendation, you may use the   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote   this message to a WARNING and allow your design to continue.   < PIN "w_clk125_out_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; > 
My 50 MHz signal is passing through two BUFIO2 that generates signals for OSERDES2, divclk and OSERDES strobe signals.
 
How do I resolve this error using DCM to generate 125MHz clock signal and passing through two BUFIO2

Thanks
Mustafa
 
 

嗨鲍勃，
感谢您的答复，
每个引脚的比特率 - 输出到DAC的数据是多少？
每个引脚的比特率是每个引脚17兆位数据输出（DDR）。
我用50MHz系统时钟测试了串行因子为（4：1）的系统，它在DAC上实现了100MSPS，这很好用。
如果您使用的序列化因子是偶数（例如8：1），则可能在SDR或DDR模式下使用OSERDES块进行序列化
如果我理解你一旦序列化因子是偶数，那么OSERDES可以在DDR模式下运行。
那么IOSERDES中的序列化因子定义了比特率操作SDR / DDR？
我希望我做对了。
我也遇到的另一个问题是，如何使用DCM生成的时钟信号作为OSERDES的输入。
UG 382表示在SDR操​​作中使用的PLL基本时钟实现。
有没有办法将125Mhz时钟信号转发到OSERDES块？
问候
穆斯塔法



以下为原文

Hi Bob,
 
Thank you for your response,

• What is the bit rate -- per pin -- of the data output to the DAC?
  

bit rate per pin is 17 megabit data output (DDR) per pin. I have tested the system with serialiation factor of (4:1) with 50MHz system clock, where it achieves 100MSPS on DAC and this works fine.
 

• If the serialisation factor you are using is an even number (e.g. 8:1), you might be using the OSERDES blocks in either an SDR or DDR mode for serialisation
  

if I understand you right once the serialisation factor is even then OSERDES can OPERATE in DDR mode. 
So the serialisation factor within the IOSERDES define the bitrate operation either SDR/DDR? I hope I got this right. 
 
 
Another issue that I am having as well, How can I use the DCM generated clock signal as an input to OSERDES.
UG 382 indicates PLL base clock implementation used in SDR operations. 
 
Is there any way of  forwarding 125Mhz clock signal to OSERDES block?
 
Regards
Mustafa
 
 
 
 
 

我希望通过14位DAC接口实现250MSPS，因此我的比特率将是每引脚17MSPS。
通过这个声明，您已经明确表示您几乎没有硬件知识。
我们可以回答问题，但是你会有一个看似无穷无尽的问题。
您需要一位知识渊博的讲师或导师，从中学习和指导。
与站在你身边的人一起指导你，你会学得更好，更快。
如果您告诉我们您计划使用哪种DAC，我们可以为您提供具体的建议。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I want to achieve 250MSPS with 14-bit DAC interface so my bit rate is  is going to be 17MSPS per pin.
 
With this statement you have made it clear you have very little hardware knowledge.  We can go round and about answering question after question, but you will have a seemingly endless stream of questions.  You need a knowledgeable instructor or mentor from which to learn and to be guided.  You will learn much better and much faster with someone standing by your side to guide you.
 
If you tell us which DAC you are planning to use, we can hopefully provide specific recommendations for you.
 
-- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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嗨Bob，Sory因为我缺乏知识，我愿意学习并感谢您分享您的宝贵知识。我正在使用模拟设备AD9117 DAC.Thanks



以下为原文

Hi Bob,
Sory for my lack of knowledge, i am willing to learn and thank you for sharing your valuable knowledge.
I am using Analog devices AD9117 DAC.

Thanks

AD9117是一款并行接口双DAC。
串行时钟是字速率的1/2。
最大串行时钟频率为125MHz，最大数据速率为250 Mbits / sec。
在这些数据速率和时钟频率下，您没有令人信服的理由去打扰OSERDES块。
如果您的核心逻辑运行在250MHz（这完全在Spartan-6功能范围内），您也不需要打扰ODDR块。
简单的寄存器 - 寄存器传输就足够了。
由于您不熟悉硬件设计和FPGA设计，我建议您尽可能简化设计。
随着您获得信心和知识，您成功提高设计复杂性的能力应该会增长。
初始设计者的第一直觉是为设计中的各种模块或功能生成各种频率的时钟。
这应该被抵制。
简单的方法：使用PLL将50MHz输入时钟乘以250MHz，并将状态机和数据通路设计为250MHz。
如果您需要或想要更慢的工作频率，请考虑生成时钟使能，以便在使用单个250MHz全局时钟时提供更低的工作速率。
这是一种更优雅，更简单的设计方法，而不是生成多个时钟，并确定在各个时钟域之间交叉时如何管理时序余量。
请注意，AD9117是双通道DAC，I和Q DAC的源数据在DAC的单个并行数据输入总线上进行时间复用。
因此，每个DAC的最大字速率为125MWords / s，而不是250MWords / s。
如果您只想驱动2个DAC中的1个，那么您可以在FPGA中使用125MHz（而不是250MHz）的全局系统时钟。
如果你这样做 - 这既是简化又是优化 - 那么你将使用ODDR模块将125MHz时钟从FPGA转发到DAC。
如果您对此感兴趣，请在论坛和Spartan-6文档中搜索“时钟转发”，这个主题已经在这些论坛中进行了彻底的讨论和描述。
我希望这对你有帮助。
祝你学习顺利，请找一位经验丰富的同事来帮助你。
随着近在咫尺的人，您将学得更快更好。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
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我没有支付论坛帖子的费用。
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以下为原文

AD9117 is a parallel interface dual DAC.  The serial clock is 1/2 the word rate.  Maximum serial clock frequency is 125MHz, and the maximum data rate is 250 Mbits/sec.
 
At these data rates and clock frequency, you do not have a compelling reason to bother with OSERDES blocks.  If your core logic is running at 250MHz (which is well within Spartan-6 capabilities), you do not need to bother with ODDR blocks, either.   Simple register - register transfers will be sufficient.
 
As you are new to hardware design and FPGA design, I would suggest keeping your design as simple as possible.  As you gain confidence and knowledge, your ability to successfully increase design complexity should grow.
 
The first instinct of a beginning designer is to generate a variety of clocks of varying frequency for various modules or functions in the design.  This should be resisted.
 
The simple approach:  Use a PLL to multiply the 50MHz input clock to 250MHz, and design your state machines and datapaths to operate at 250MHz.  If you need or want slower operating frequencies, consider generating clock enables to provide lower operating rates while using the single 250MHz global clock.  This is a more elegant and simpler design approach than generating multiple clocks and figuring out how to manage timing margins when crossing between the various clock domains.
 
Note that the AD9117 is a dual DAC, with the source data for the I and Q DACs time multiplexed on the single parallel data input bus to the DAC.  So the maximum word rate for each DAC is 125MWords/s, not 250MWords/s.
 
If you only wish to drive 1 of the 2 DACs, then you could get by with a 125MHz (instead of 250MHz) global system clock in the FPGA.  If you do this -- and this is both a simplification and an optimisation -- then you would use an ODDR block for forwarding the 125MHz clock from the FPGA to the DAC.  If you are interested in this, then search the forums and the Spartan-6 documentation for "clock forwarding", a subject which has been thoroughly discussed and described in these forums.
 
I hope this is a help to you.  Good luck in your studies, and please seek out an experienced colleague to assist you.  You will learn faster and better with someone close at hand.
 
-- Bob Elkind
SIGNATURE:
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Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

感谢Bob的信息，
我明白你在说什么。
我还想知道我们是否可以将DCM生成的时钟信号路由到两个BUFIO2到OSERDES2？
如何在DDR模式下使用OSERDES，同时提供DCM生成的时钟信号？我也想知道这一点，或者我们是否必须在SDR模式下使用OSERDES，使用PLL时使用两次tw时钟。
谢谢



以下为原文

Thanks for the information Bob,
 
I do understand what you are saying.
 
I still would like to know if we can route DCM generated clock signal usign two BUFIO2 to OSERDES2? How can I use the OSERDES in the DDR mode while supplying DCM generated clock signal is it possible? I want know this as well, or do we have to use OSERDES in SDR mode and twice tw clock using PLL.
 
Thanks 
 

我还想知道我们是否可以将DCM生成的时钟信号路由到两个BUFIO2到OSERDES2？
如何在DDR模式下使用OSERDES，同时提供DCM生成的时钟信号？我也想知道这一点，或者我们是否必须在SDR模式下使用OSERDES，使用PLL时使用两次tw时钟。
两个建议：
1.阅读用户指南（特别是UG382和UG381）以获得问题的答案。
我很确定答案就在那里。
2.在ISE中对您的设计进行编码并进行尝试。
使用ISE作为指导，了解Spartan-6平台的工作原理和功能。
看起来简单地与AD9117 DAC接口并不是您唯一的兴趣或目标。
您可能想详细说明您的具体兴趣。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I still would like to know if we can route DCM generated clock signal usign two BUFIO2 to OSERDES2? How can I use the OSERDES in the DDR mode while supplying DCM generated clock signal is it possible? I want know this as well, or do we have to use OSERDES in SDR mode and twice tw clock using PLL.
 
Two suggestions:

 
1.  Read the User Guides (specifically UG382 and UG381) for the answers to your questions.  I'm pretty sure the answers are in there.

 
2.  Code up your design in ISE and try it.  Use ISE as your guide to what will work and what will not work on Spartan-6 platform.

 
It seems that simply interfacing to an AD9117 DAC is not your only interest or objective.  You might want to spell out your specific interests.

 
-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.