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你好,
我有一个我无法理解的引脚分配问题。 我使用PlanAhead13.2来创建引脚分配,然后使用UCF文件为XC6SLX45-2CSG324C。 假设存储体1和3不能用作差分输出,我将差分输入和输出连接到存储体0,将DDR接口连接到存储体3,将并行引导NOR闪存连接到存储体1和2(因为它具有专用引脚 两个银行),然后我继续将另一部分LVDS信号连接到bank 2.我已成功连接输出对,但堆叠了输出对的连接。 当我将输出对拖到第2行时,我收到一个弹出式按摩,这意味着“无法放置任何端口。请尝试顺序放置以获得更详细的原因。” 我注意到如果将输出对拖到bank 0,就可以了......但是我需要将它连接到bank 2.任何人都有想法? 谢谢, 安德烈 以上来自于谷歌翻译 以下为原文 Hello, I have a pin assignment problem that i can not understand. I do use PlanAhead13.2 in order to create pin assignment and then UCF file for XC6SLX45-2CSG324C. Assuming that bank 1 and 3 cannot be used as a differential output I have connected differential inputs and outputs to bank 0, connected a DDR interface to bank 3, connected a parallel boot NOR flash to bank 1 and 2(as it has dedicated pins on both banks), then I proceeded with connection of another portion of LVDS signals to bank 2. I have succeeded with connection of output pairs, but stacked with connection of output pairs. I receiving a pop up massage when I drag an output pair to bank 2 which means "Can not place any port. Try a sequential placement for a more detailed reason." I noticed if a drag the output pair to bank 0, it is OK...However I need to connect it to bank 2. Anyone have an idea? Thanks, Andrey |
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3个回答
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嗨,
你的问题描述太模糊了。 是否正在尝试使用PlanAhead IO Planning工具为合成网表分配引脚? 请至少发布您的设计和ucf的pin列表,如果有的话。 合成的顶层设计将有助于重现您的问题。 RGDS, 詹恩 以上来自于谷歌翻译 以下为原文 Hi, Your problem description is too vague. Are trying to assign pins against synthesized netlist using PlanAhead IO Planning tool? Please post atleast the pin list of your design and ucf, if you had one. The synthesized top level of your design would help to reproduce your problem. Rgds, Janne |
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你好Janne,
我已经解决了这个问题,但只是为了记录而解释。 NORflash接口使用bank 1和2,而I / O定义为LVCMOS33,因为我使用3.3V作为VCCO。 在bank 1上,我成功连接了INPUT LVDS信号,用LVDS25标准定义。 当我开始将带有LVDS25标准的OUTPUT LVDS信号连接到bank 2(其中一些NOR闪存引脚已经与LVCMOS33连接)时,我遇到了问题,这是因为不同的电压标准。 因此,解决方案是将所有电压标准定义为2.5V,为VCCO提供3.3V电压。 希望很清楚。 问候, 安德烈 以上来自于谷歌翻译 以下为原文 Hello Janne, I have solved this issue, but will explain just for the record. NOR flash interface uses both banks 1 and 2 while I/Os are defined as LVCMOS33, as I use 3.3V for VCCO. On bank one I have successfully connected INPUT LVDS signals, defined with LVDS25 standard. When I started to connected OUTPUT LVDS signals with LVDS25 standard to bank 2(where some NOR flash pins were already connected with LVCMOS33) I got a problem and it is because different voltages standards. So the solution is to define all voltage standards as 2.5V supplying 3.3V to the VCCO. Hope it is clear. Regards, Andrey |
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Spartan-6确实有LVDS33标准。我认为你可以使用它.BTW,差分终端在2.5V VCCO下不会是100欧姆。
以上来自于谷歌翻译 以下为原文 Spartan-6 does have LVDS33 standard. I think you can use this. BTW, the differential termination won't be 100ohm under 2.5V VCCO. |
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