请问Spartan 6 LVDS和DDR接口哪个最合适？

嗨，
请参考UG388获取DDR2引脚放置指南。
由于Spartan-6中的MCB是硬块，您只能选择所有固定的库存，您将在... example_design / par文件夹中获得一个.ucf，您可以将其用作参考。
对于LVDS，我认为可以使用任何银行。
请参考以下链接
http://forums.xilinx.com/t5/7-Series-FPGAs/LVDS-18-with-LVCMOS-18-in-same-bank/td-p/353085
http://forums.xilinx.com/t5/7-Series-FPGAs/Problem-with-signal-standards-LVDS-25-and-LVCMOS33/td-p/370129
您可以运行包含MIG和LVDS的示例设计，并检查时序报告，该报告为您提供了基于您可以继续执行的操作的线索。
希望这可以帮助
问候，
Vanitha。
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以下为原文

Hi,
 
Please refer UG388 for DDR2 pin placement guideliness.
As MCB in Spartan-6  is  hard block you can select only the bank rest all are fixed, you will get a .ucf in ...example_design /par folder which you can use it as reference.
For LVDS i think any bank can be used.
Please refer below links
http://forums.xilinx.com/t5/7-Series-FPGAs/LVDS-18-with-LVCMOS-18-in-same-bank/td-p/353085
http://forums.xilinx.com/t5/7-Series-FPGAs/Problem-with-signal-standards-LVDS-25-and-LVCMOS33/td-p/370129
 
You can run the example design with MIG and LVDS included and check the timing report which gives you a clue on what to do based on which you can go ahead.
 
Hope this helps
 
Regards,
Vanitha.
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anbuub写道：
现在我想将ADC（LVDS接口）连接到任何bank（0,1,2）。由于ADC非常HighSpeed，我想知道哪个bank最适合接口。
银行都是相同的w.r.t.
高速接口能力。
----------------------------是的，我这样做是为了谋生。



以下为原文

anbuub wrote:
 
now i want to interface the ADC (LVDS interface) to anyther bank(0,1,2) .Since the ADC is very HighSpeed i would like to know which bank is best for interface.

The banks are all identical w.r.t. high-speed interface capability. 
----------------------------Yes, I do this for a living.

非常感谢..



以下为原文

Thanks lot..

非常感谢



以下为原文

Thanks lot