怎么使用FX3 GPIF-II的同步从设备FIFO写模式

你好，
当我调试我的逻辑接口FX3时，我注意到一些我想确认的东西。我们使用的同步从FIFO写模式的FX3 GPIF - II。
根据FX3规格（cyu***3014.pdf page-21），有两种不同的发行方式之一pktend，与去年的数据和一个没有数据（ZLP）。与FX2，fifoaddr必须提出一个周期的早期写数据。
在第一种情况下（pktend W /数据）pktend似乎assocating与写入数据的联系地址，这是在前一个周期的地址。然而，在后者的情况下（pktend W / O数据）的pktend是结合在同一周期的地址。
我的设计管道的地址和数据，在最后一个数据周期的地址可能不保持不变，从以前的周期。
我想知道的是，在第一种情况下，pktend（pktend W /数据）是结合周期是一致的数据写在前一个周期或地址。
如果pktend是结合在同一周期的地址，柏树应该在Fx3文档中提及这样的限制。否则，它会创建一个调试困难神秘的问题。
谢谢你的关注。安艺-



     以下为原文
  Hello,
    While I was debugging my logic that interfaces to the FX3, I noticed something I would like to confirm. We are using Synchronous Slave FIFO Write Mode of the FX3 GPIF-II.
    According to the FX3 spec (CYUSB3014.pdf page-21), there are two different ways of issuing PKTEND, one with last data and one without data (ZLP). Unlike FX2, FIFOADDR must be presented a cycle earlier to write data.
    In the first case (PKTEND w/ data) PKTEND seems assocating with the address the write data is associating with, which is the address in the previous cycle. However, in the latter case (PKTEND w/o data) the PKTEND is associating with the address in the same cycle.
    As my design pipelines the address and the data, the address in the last data cycle *may* not stay the same from the previous cycle.
    I would like to know whether the PKTEND in the first case (PKTEND w/ data) is associating with the address in the previous cycle or the address in the cycle that is coincident to the write data.
    If the PKTEND is associating with the address in the same cycle, Cypress should mention such restriction in the FX3 documentation. Otherwise, it would create a hard-to-debug mysterious problem.
    Thank you for your attention.
Aki-