代码在fpga中给出错误的结果

我找到了错误的主要原因。
查找代码无法以100 MHz的时钟速度按预期工作，但如果我将此时钟速度降低到50 MHz，那么我得到的结果是正确的。
所以问题不在于多路复用器的代码而是时钟速度的兼容性。
问候，
Koyel
在原帖中查看解决方案



以下为原文

I have found the main cause of the error. The lookup code is not able to work as expected with a clock speed of 100 MHz but if I reduce this clock speed to 50 MHz then I am getting correct result. So the problem was not in the code of multiplexer but the clock speed compatibility.
 
Regards,
Koyel
View solution in original post

嗨，
您可以尝试附加存档文件夹吗？
此外，请确保您的设计是正确的约束。
谢谢，Anusheel -----------------------------------------------
-  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - 搜索
在论坛上发布查询之前，与您的设备和工具相关的文档/答案记录。搜索相关论坛并确保您的查询不会重复。请将帖子标记为“接受为解决方案”，以防它有助于解决您的查询。帮助
回答 - >给予Kudos ---------------------------------------------
--------------------------------------------------



以下为原文

Hi,
 
Can you try attaching the archive folder?
Also, make sure your design is properly constraint.
 
Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

我正在附加我的项目的vhdl文件。
我把它压缩了。
顶级实体是testdesign3_100v3.vhd
模拟给出了正确的结果。
输出为SPDPout。
模拟必须在停止之前运行30802002或更多时钟脉冲。这是RFaddress信号，初始化为31必须转到下一个31然后再到0，然后停止模拟并看到SPDPout。
请告诉我为什么FPGA没有给出模拟给出的结果。
在30802000时钟脉冲SPDPout给出00804340d7168acc后，在下一个时钟脉冲给出7d43bfa5e348e000。
这不会出现在FPGA输出中。
如果缺少某些文件，请告诉我。
问候，
Koyel
xilinx.zip 18 KB



以下为原文

I am attaching the vhdl files of my project. I have zipped it. The top entity is testdesign3_100v3.vhd
 
Simulation is giving correct result. The output is SPDPout.  The simulation has to run for 30802002 or more clock pulses before stopping That is RFaddress signal, initialized to 31 has to go to next 31 and then to 0 before stopping the simulation and seeing the SPDPout.
 
Please let me know why FPGAs are not giving the results that simulation is giving. After 30802000 clock pulses SPDPout is giving 00804340d7168acc and in the next clock pulse its giving 7d43bfa5e348e000.
 
This is not appearing in FPGA output. Please let me know if some file is missing.
 
Regards,
Koyel
            xilinx.zip ‏18 KB

@ koyel81什么不行？
你做过路线后时序模拟吗？
要附加多个文件，我建议您将其存档为zip并附加
-Pratham ------------------------------------------------
----------------------------------------------请注意 - 请
如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-
--------------------------------------------------
-----------------------



以下为原文

@koyel81 What is not working? Have you done post-route timing simulation? To attach multiple files i would recommend you to archive it in zip and attach
-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

嗨，
我没有收到关于敏感度列表的任何警告。
我在每个报告中使用关键字进行搜索，但其中没有“敏感度”一词。
如果我的信号比列表中所需的信号多吗？



以下为原文

Hi,
 
I have not received any warning on sensitivity list. I searched using the keyword in each report and it doesn't have the word "sensitivity" in it. Does it matter if I have more signals than needed in the list?

是的，感觉列表很重要。 
你得到了他们的错误，预先P＆amp; R模拟和合成可以/将分歧。
至于警告， 
是的，只是在vivado和ISE中尝试了lookup.vhd，正如你所说，它们没有显示任何警告！
惊人，
除非你正在运行一些谎言modelsim然后我认为你更加宽松！
让我大开眼界。
你还需要研究图书馆， 
你正在使用std_logic_unsigned，numeric_std和std_logic_1164， 
就我所见，它不会成为查询中的问题，但是形状不好，
http://cdstahl.org/?p=761
建议你看看你们公司的编码标准并获得一本好书
也
使用rising_edge not（clk'event和clk ='0'） 
并注意一个进程最多可以有一个rising_edge命令， 
想想合成器将如何通过两个rising_edge命令来实现块？



以下为原文

yes, sensetivity lists do matter.
  you get them wrong and pre P&R simulation and synthesis can / will diverge.
 
 
As for warnings,
   yes well , just tried lookup.vhd in vivado and ISE , and as you say, they shows no warnings !
 
Amazing, 
 
unless you are runing something liek modelsim I think you are onto a looser then !
 
an eye opener to me.
 
You also need to look into libraries,
   you are using std_logic_unsigned, numeric_std and std_logic_1164, 
   
wont be a probelm in lookup as far as I can see, but teribaly bad form,
 
http://cdstahl.org/?p=761
 
suggest you look at your companies codding standard and get a good book or two 
 
 
 
Also
 
use rising_edge not (clk'event and clk = '0')
   
and note that a process can have a maximum of one rising_edge command in it, 
   think how would the synthesiser impliment the block with two rising_edge commands in it ?
 
 
 
    

koyel81写道：
我正在附加我的项目的vhdl文件。
我把它压缩了。
顶级实体是testdesign3_100v3.vhd
模拟给出了正确的结果。
输出为SPDPout。
模拟必须在停止之前运行30802002或更多时钟脉冲。这是RFaddress信号，初始化为31必须转到下一个31然后再到0，然后停止模拟并看到SPDPout。
请告诉我为什么FPGA没有给出模拟给出的结果。
在30802000时钟脉冲SPDPout给出00804340d7168acc后，在下一个时钟脉冲给出7d43bfa5e348e000。
这不会出现在FPGA输出中。
如果缺少某些文件，请告诉我。
哪个文件是测试台？
您应该学习如何构建您的设计。
将可合成源放在它们自己的目录中，与测试平台源分开，并且还与Xilinx工具的文件（xise，ucf等）分开。
----------------------------是的，我这样做是为了谋生。



以下为原文

koyel81 wrote:
I am attaching the vhdl files of my project. I have zipped it. The top entity is testdesign3_100v3.vhd
 
Simulation is giving correct result. The output is SPDPout.  The simulation has to run for 30802002 or more clock pulses before stopping That is RFaddress signal, initialized to 31 has to go to next 31 and then to 0 before stopping the simulation and seeing the SPDPout.
 
Please let me know why FPGAs are not giving the results that simulation is giving. After 30802000 clock pulses SPDPout is giving 00804340d7168acc and in the next clock pulse its giving 7d43bfa5e348e000.
 
This is not appearing in FPGA output. Please let me know if some file is missing.
 

Which file is the test bench? You should learn how to structure your designs. Put synthesizable sources in their own directory, separate from the test bench sources, and also separate from the Xilinx tools' files (xise, ucf, etc).
----------------------------Yes, I do this for a living.