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我对FM S-14 daugther卡有一些疑问。 这是我从更快的技术网站下载的参考设计。 及其pdf文件是FM S-14 daugther卡的手册。 某些引脚在S-14手册中定义,在参考设计中,它们连接到VIO。 并为他们提供了一个ucf文件。 我想在Kintex7评估板上使用此卡。 但我不知道在我的ucf文件中定义ucf文件参考设计中的所有端口是否重要? 实际上,通过关注S-14手册和参考设计的表格,我不知道S-14的哪个引脚定义至关重要? 下面的代码是S-14参考设计的top_module代码的一部分我无法理解。 -------------------------------------------------- ------------- --FMC卡 -------------------------------------------------- ------------- -------------------------------------------------- ------------------------------- - 为FMC用户切换信号推断三个状态IO 进程(fmc_user_switch_en,fmc_user_switch_o) 开始 for fmc_user_switch_o'range循环中的ii if(fmc_user_switch_en(ii)='1')然后 fmc_user_switch(ii)CONTROLfmc, ASYNC_IN => ASYNC_IN_fmc, ASYNC_OUT => ASYNC_OUT_fmc); icon_name:图标 港口地图( CONTROL0 => CONTROL0, CONTROL1 => CONTROLfmc); 你能指导我如何使用这款FMC卡吗? 谢谢 以上来自于谷歌翻译 以下为原文 Hello, I've some question about FM S-14 daugther card. This is ref design that I've downloaded from faster technology website. and its pdf file is manual of FM S-14 daugther card. some pins are defined in S-14 manual and in ref design they were connected to VIO. and there is a ucf file for them. I want to use this card on Kintex7 evaluation board. But I don't know is it important to define all the port in ucf file ref design in my ucf file or not? actually, by attention to the tables of S-14 manual and ref design I don't know which pin definition of S-14 is vital? the below code is some part of top_module code of S-14 ref design I can't understand it. -----------------------------------------------------------------FMC Card------------------------------------------------------------------------------------------------------------------------------------------------ -- Infer three state IO for the FMC user switch signalsprocess (fmc_user_switch_en, fmc_user_switch_o)begin for ii in fmc_user_switch_o'range loopif (fmc_user_switch_en(ii)='1') thenfmc_user_switch(ii) <= fmc_user_switch_o(ii);elsefmc_user_switch(ii) <= 'Z';end if;end loop;end process;-- Group signals by SFPprocess (fmc_sfp_tx_fault,fmc_sfp_los)beginfor ii in fmc_sfp_los'range loopfmc_sfp_ins(ii*2+1 downto ii*2) <= (fmc_sfp_tx_fault(ii),fmc_sfp_los(ii));end loop;end process;process (fmc_sfp_outs)beginfor ii in fmc_sfp_rate_sel'range loopfmc_sfp_tx_disable(ii) <= fmc_sfp_outs(ii*3+2);fmc_sfp_rate_sel(ii) <= fmc_sfp_outs(ii*3+1);fmc_sfp_mod_def0(ii) <= fmc_sfp_outs(ii*3);end loop;end process; -- ASYNC_IN <= std_logic_vector'(std_logic_vector(fmc_user_switch),fmc_sfp_ins); ASYNC_IN_fmc(ASYNC_IN_fmc'left) <= independent_clock_bufg; ASYNC_IN_fmc(ASYNC_IN_fmc'left-1 downto ASYNC_IN_fmc'left - fmc_user_switch'length) <= fmc_user_switch; ASYNC_IN_fmc(fmc_sfp_ins'range) <= fmc_sfp_ins; --(fmc_led,fmc_user_switch_o,fmc_user_switch_en,fmc_sfp_outs) <= ASYNC_OUT; fmc_led <= ASYNC_OUT_fmc(fmc_led'length + fmc_user_switch_o'length + fmc_user_switch_en'length + fmc_sfp_outs'length - 1 downto fmc_user_switch_o'length + fmc_user_switch_en'length + fmc_sfp_outs'length); fmc_user_switch_o <= ASYNC_OUT_fmc(fmc_user_switch_o'length + fmc_user_switch_en'length + fmc_sfp_outs'length - 1 downto fmc_user_switch_en'length + fmc_sfp_outs'length); fmc_user_switch_en <= ASYNC_OUT_fmc(fmc_user_switch_en'length + fmc_sfp_outs'length - 1 downto fmc_sfp_outs'length); fmc_sfp_outs <= ASYNC_OUT_fmc(fmc_sfp_outs'range);viofmc_name : vio_fmc port map ( CONTROL => CONTROLfmc, ASYNC_IN => ASYNC_IN_fmc, ASYNC_OUT => ASYNC_OUT_fmc );icon_name : icons port map ( CONTROL0 => CONTROL0, CONTROL1 => CONTROLfmc); Could you please guide me how can I use of this FMC card? Thanks |
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6个回答
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您发布的代码不包含任何顶级IO端口,并且必须使用正确的IOSTANDARD和LOC属性约束那些端口,并且您没有说明您正在使用哪个运营商卡。
FMC接口是通用接口,Xilinx载板卡(如KC705)使用通用接口名称(例如LA00_CC_P)进行记录。 您需要使用FM-S14原理图或用户指南来确定模块特定接口名称到FMC通用接口名称的映射,然后将这些名称与载卡用户指南中的文档进行匹配,以确定FPGA引脚LOC约束 必须适用。 FM-S14文档还应指定每个接口引脚所需的IOSTANDARD。 如果他们已完成FM-S14和您正在使用的运营卡的此练习,您也可以询问更快的技术支持。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The code that you posted does not include any top level IO ports and it is those ports that must be constrained with the correct IOSTANDARD and LOC attributes and you have not said which carrier card you are using. The FMC interface is generic interface and the Xilinx carrier cards, like the KC705, are documented using the generic interface names, such as LA00_CC_P. You will need to use the FM-S14 schematic or user guide to determine the mapping of the module specific interface names to the FMC generic interface names and then match these against the documentation in the carrier card user guide to determine the FPGA pin LOC constraint that must be applied. The FM-S14 documentation should also specify what IOSTANDARD is required for each of the interface pins. You could also ask Faster Technology support if they have already completed this exercise for the FM-S14 and the carrier card that you are using. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.comView solution in original post |
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嗨,
您可以从KC705用户指南主UCF获取帮助。 检查UCF中的FMC引脚,如第77页开头所述-http://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf Pg 75,Pg 56,57中的进一步参考文献 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, You can take help from the KC705 user guide master UCF. Check for the FMC pins in the UCF as given in Pg 77 onwards - http://www.xilinx.com/support/documentation/boards_and_kits/kc705/ug810_KC705_Eval_Bd.pdf Further references in Pg 75, Pg 56,57 Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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你好,
谢谢。 我读过它们。 我对控制FM-S14卡的soem IO引脚的上述代码感到困惑。 你能指导我上面的代码吗? 问候 以上来自于谷歌翻译 以下为原文 Hello, thanks. I've read them. I'm confused about above code that controls soem IO pins of FM-S14 card. Could you please guide me about above code? Regards |
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您发布的代码不包含任何顶级IO端口,并且必须使用正确的IOSTANDARD和LOC属性约束那些端口,并且您没有说明您正在使用哪个运营商卡。
FMC接口是通用接口,Xilinx载板卡(如KC705)使用通用接口名称(例如LA00_CC_P)进行记录。 您需要使用FM-S14原理图或用户指南来确定模块特定接口名称到FMC通用接口名称的映射,然后将这些名称与载卡用户指南中的文档进行匹配,以确定FPGA引脚LOC约束 必须适用。 FM-S14文档还应指定每个接口引脚所需的IOSTANDARD。 如果他们已完成FM-S14和您正在使用的运营卡的此练习,您也可以询问更快的技术支持。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 The code that you posted does not include any top level IO ports and it is those ports that must be constrained with the correct IOSTANDARD and LOC attributes and you have not said which carrier card you are using. The FMC interface is generic interface and the Xilinx carrier cards, like the KC705, are documented using the generic interface names, such as LA00_CC_P. You will need to use the FM-S14 schematic or user guide to determine the mapping of the module specific interface names to the FMC generic interface names and then match these against the documentation in the carrier card user guide to determine the FPGA pin LOC constraint that must be applied. The FM-S14 documentation should also specify what IOSTANDARD is required for each of the interface pins. You could also ask Faster Technology support if they have already completed this exercise for the FM-S14 and the carrier card that you are using. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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你好,谢谢你的回复。
我正在研究KC705板。 所以你的意思是这些端口只是在ucf文件中定义并将它们连接到运营商卡。 谢谢 以上来自于谷歌翻译 以下为原文 Hi, Thanks for your reply. I'm working on KC705 board. So you mean these ports just shoud define in ucf file and connect them to carrier card. Thanks |
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是的,就像任何设计一样。
------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Yes, just like any design.------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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