如何在配置期间添加额外的cclk周期

男，
在比特流结束后添加伪数据将产生“额外的时钟周期”。
http://www.google.com/url?sa=t&rct=j&q=extending%20xilinx%20bitstream&source=web&cd=5&cad=rja&ved=0CE8QFjAE&url=http%3A%
2F％2Fwww.xilinx.com％2Fsupport％2Fdocumentation％2Fapplication_notes％2Fxapp583-FPGA-configuration.pdf＆安培; EI = gMRQUdWYIcK6igLIi4CABw＆安培; USG = A ...
此外，比特流的末尾也包含启动选项。
这些中的任何一个都可以被认为是“添加额外的cclk周期”。
一个添加更多数据（因此更多时钟），其中启动选项控制在启动期间最后一个时钟周期发生的事情。
我怀疑你需要前者（更多的数据来创造更多的时钟），而不是后者。
但我不能确定，因为我不知道你在哪里读到这个，谁告诉你有关额外的cclk周期的人。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

m,
 
Adding dummy data after the end of the bitstream will generate "extra clock cycles."
 
http://www.google.com/url?sa=t&rct=j&q=extending%20xilinx%20bitstream&source=web&cd=5&cad=rja&ved=0CE8QFjAE&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fapplication_notes%2Fxapp583-fpga-configuration.pdf&ei=gMRQUdWYIcK6igLIi4CABw&usg=A...
 
Also, the end of the bitstream contains startup options, too.
 
Either of these may be considered "add extra cclk cycles."
 
One adds more data (and hence more clocks), where the startup options control what happens on what clock cycle at the end during startup.
 
I suspect you need the former (more data to create more clocks), and not the latter.  But I can't be sure, because I don't know where you read that, who who told you about extra cclk cycles.
Austin Lesea
Principal Engineer
Xilinx San Jose

markjackson写道：
我正在努力使用不使用平台闪存编程的自定义主板。
我可以通过影响编程FPGA和闪存，但fpga无法启动。
时钟正常，有明显的数据传输到设备。
广泛的谷歌搜索显示，添加额外的时钟周期可以解决这个问题，但我无法在任何地方找到如何做到这一点。
请求白痴指导！
您是在主串行模式下配置FPGA吗？
这不需要任何额外的东西;
位文件应该包含所有必需的内容，FPGA将根据需要生成尽可能多的CCLK。
在从串行模式中，外部主设备（可能是微控制器）正在向FPGA发送配置数据，您必须确保监控DONE和INIT_B信号并继续生成CCLK，直到DONE变为高电平为止。
----------------------------是的，我这样做是为了谋生。



以下为原文

markjackson wrote:
I'm struggling with a custom board not programming from platform flash.
 
I can programm theFPGA and the flash from impact, but the fpga is not booting. Clock is OK and there is clearly data transferring to the device. Extensive googling shows that adding extra clock cycles may solve this but I can't find how to do this anywhere.
 
Idiot-proof guide required please!

Are you configuring the FPGA in master-serial mode? That shouldn't need anything extra; the bit file should have everything necessary and the FPGA will generate as many CCLKs as necessary.
 
In slave serial mode, where an external master, perhaps a micro, is sending configuration data to the FPGA, you have to make sure you monitor the DONE and INIT_B signals and keep generating CCLKs until DONE goes high.
----------------------------Yes, I do this for a living.

您的FPGA位流需要具有正确的启动配置，否则将无法启动。
看一下bitgen“启动选项”配置设置。
我相信它默认为JTAG，这意味着如果你使用JTAG从影响加载它将会起作用。
您需要将其更改为CCLK以从闪存中加载它。
还要确保选中“Enable Internal Done Pipe”和“Drive Done Pin High”选项，以便DONE引脚实际发出配置结束的信号。
布鲁诺



以下为原文

Your FPGA bit stream needs to have the proper startup configuration or it won't start.
Take a look at the bitgen "Startup Options" configuration settings.
I believe that it defaults to JTAG, meaning that it will work if you load it from impact using JTAG.
You need to change it to CCLK to load it from the flash.
Also make sure that the options "Enable Internal Done Pipe" and "Drive Done Pin High" are checked, so that the DONE pin actually signals the end of the configuration.
 
Bruno

不好意思！
事实上我的cclk线不行。
跟踪错误意味着戴维南终端没有绑定到3.3V，所以它在整个节目中响起。
电路板现在配置，除非我探测它！
必须是电容的东西，但至少是进步。
为什么那条线如此** sensitive **敏感？



以下为原文

Sussed it!
 
In fact my cclk line was not OK. A tracking error meant the thevenin terminations were not tied to 3.3V so it was ringing all over the show. The board now configures, except only when I probe it!
 
Must be a capacitance thing, but at least progress.
 
Why is that line so **bleep** sensitive?

我很高兴你找到了这个问题。
配置问题也让我疯狂。
至少在Spartan3和Spartan6设备上，这条线根本不是“如此** ble **敏感”。
至少没有（到目前为止）探测器弄乱了。
FPGA可以以相当高的速度进行计时，因此如果您有太多振铃或错误的电平，您可能会意外地使其注册额外的时钟。
这也意味着如果你有一个很长的上升时间斜率（大到一个上拉？）你也可以多时钟。
检查您的电路板设计。
另请查看相关器件的配置指南，查看推荐的上拉电阻以及FPGA内部可以启用的上拉电阻。
布鲁诺



以下为原文

I am glad you found the issue.
Configuration problems drive me nuts too.
 
That line is not "so **bleep** sensitive" at all, at least on Spartan3 and Spartan6 devices.
At least not (by far) to the point that a probe messes things up.
The FPGA can be clocked at pretty high speeds, so if you have too much ringing or wrong levels you can accidentally cause it to register extra clocks.
This also means that if you have a long slope for rise time (to large a pullup?) you could also multi-clock.
Check your board design.
Also check the configuration guide for the device in question and look for recommended pullup resistors as well as pullups internal to the FPGA that could be enabled.
 
Bruno
 

男，
它被称为“信号完整性”工程，如果你忽略它，它就会咬你。
受控阻抗线（布局）和适当的终端。
提供PCB用户指南。
并获得一个很好的SI CAD工具（我使用Hyperlynx）。
你不需要重新做的第一块板就可以节省你的工具成本。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

m,
 
It is calleed "signal integrity" engineering, and if you ignore it, it eill bite you.
 
Controlled impedance lines (layout) and proper terminations.  Cosult the PCB user's guides.
 
And get a good SI CAD tool (i use Hyperlynx).
 
What the tool costs you is saved by the first board you DON'T have to re-do.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

markjackson写道：
为什么那条线如此** sensitive **敏感？
CCLK与其他时钟没有什么不同！
----------------------------是的，我这样做是为了谋生。



以下为原文

markjackson wrote:
 
Why is that line so **bleep** sensitive?

CCLK is no different from any other clock!
----------------------------Yes, I do this for a living.