配置后CCLK有效

鲍勃你好
感谢您的回答。
我已经解决了自己的问题。
我们有一个PLL在启动时没有时钟输入，所以在启动时它不会被锁定。
因为我们在ISE启动选项过程属性中选择了“等待DCM和PLL锁定”，所以使用用户设计启动了spartan，但是在启动时用于从闪存中加载位文件的IO将不会
从IO关闭。
这就是我在启动后在CCLK引脚上有时钟信号的原因。将“等待DCM和PLL锁定”设置为noWait，设计工作正常。
丹尼尔
在原帖中查看解决方案



以下为原文

Hello Bob
 
Thanks for your answer. I have solved the problem my self. We have an PLL which has at startup no clock input, so it will not be locked at startup. Because we have select the "Wait for DCM and PLL Lock" in the ISE Startup Option Process properties, the spartan was started up with the user design, but the IO's which will be used at startup for load the bitfile out of the flash will not be switched off from the IO. That was the reason I had a clock signal on the CCLK pin as well after the startup.

With setting the "Wait for DCM and PLL Lock" to noWait the design works fine.
 
Daniel
View solution in original post

您的FPGA设计是否包含用于访问SPI闪存的SPI主设备？
在DONE变高后，SPI时钟是永久运行还是仅运行几个周期（20-30）？
（DONE信号变高了吗？）
FPGA是否配置为多FPGA（即菊花链）配置？
如果是这样，下游FPGA是否配置？
- 鲍勃埃尔金德
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以下为原文

Does your FPGA design include an SPI master for accessing the SPI flash?
 
Does the SPI clock run forever, or just for a few cycles (20-30) after DONE goes high? (does the DONE signal go high?)
 
Is the FPGA configured for multi-FPGA (i.e. daisy chain) configuration?  If so, do the downstream FPGAs configure?
 
- Bob Elkind
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鲍勃你好
感谢您的回答。
我已经解决了自己的问题。
我们有一个PLL在启动时没有时钟输入，所以在启动时它不会被锁定。
因为我们在ISE启动选项过程属性中选择了“等待DCM和PLL锁定”，所以使用用户设计启动了spartan，但是在启动时用于从闪存中加载位文件的IO将不会
从IO关闭。
这就是我在启动后在CCLK引脚上有时钟信号的原因。将“等待DCM和PLL锁定”设置为noWait，设计工作正常。
丹尼尔



以下为原文

Hello Bob
 
Thanks for your answer. I have solved the problem my self. We have an PLL which has at startup no clock input, so it will not be locked at startup. Because we have select the "Wait for DCM and PLL Lock" in the ISE Startup Option Process properties, the spartan was started up with the user design, but the IO's which will be used at startup for load the bitfile out of the flash will not be switched off from the IO. That was the reason I had a clock signal on the CCLK pin as well after the startup.

With setting the "Wait for DCM and PLL Lock" to noWait the design works fine.
 
Daniel