模拟时ISE报告错误

嗨，
此功能需要使用一些库/包。
可能是一些定点包。
其中一个符合VHDL 2008标准。
如果您使用它，您的工具必​​须支持VHDL 2008。
可能存在具有类似功能的其他非标准化包。
这些必须包含在您的项目中并为您的工具编译。
检查它们是否也支持合成，除非您不只是想在测试平台中使用它。
有一个很好的模拟 
Eilert



以下为原文

Hi,
this function requires some library/package to be used.
 
Probably some fixed point package.
One is available with the VHDL 2008 standard.
If you are using that your tools must support VHDL 2008.
 
There may be other non-standardized packages with similar functionality.
These have to be included into your project and compiled for your tools.
Check out if they also support synthesis, unless you don't just want to use it in testbenches.
 
Have a nice simulation
  Eilert

你好
在代码中添加库声明
库ieee_proposed;使用ieee_proposed.fixed_pkg.all;
问候，
Prathamesh
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以下为原文

Hi
 
Add library declaration in your code
 
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
 
Regards,
Prathamesh
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-Pratham

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我的ISE版本是14.3，目标设备是virtex 6，VHDL源码分析标准是VHDL-200X，我将下面的所有包添加到我的项目中，为什么它仍然无法工作？
standard_additions_c.vhdlenv_c.vhdlstandard_textio_additions_c.vhdlstd_logic_1164_additions.vhdlnumeric_std_additions.vhdlnumeric_std_unsigned_c.vhdlfixed_pkg_c.vhdlfloat_pkg_c.vhdl



以下为原文

My ISE version is 14.3, target device is virtex 6, VHDL source analysis standard is VHDL-200X, I add all the package below into my project, why it still can't work?
 
standard_additions_c.vhdl
env_c.vhdl
standard_textio_additions_c.vhdl
std_logic_1164_additions.vhdl
numeric_std_additions.vhdl
numeric_std_unsigned_c.vhdl
fixed_pkg_c.vhdl
float_pkg_c.vhdl

我已经做到了，但仍然行不通。



以下为原文

I've already done that, but is still can't work.