错误0001：致命的内部错误

大家好，
当我开始在系统生成器中生成vhdl代码时，我收到此消息：开始生成检查模型状态检查模拟时间执行编译和生成***错误***网表生成期间发生错误.S-function'sysgen报告错误
'in'I06_vol13_DITC_sensorless_2016_04_06_loader_ver / Implementation_FPGA / transform_input_values / Register35'：Sysgen错误的摘要已写入C：/ Users / Dima / Desktop / Studium / matlab Projekte / aktuell / Changing_Force_Table / I06_vol13_DITC_sensorless_2016_04_06_loader_ver_sysgen_error.log --------
--------------------------------------------------
--------------------------------------------------
--------------------------------------------------
---
---------------------------------版本日志---------------
------------------- Version PathSystem Generator C：/Xilinx/14.7/ISE_DS/ISE/sysgenMatlab 8.5.0.197613（R2015a）C：/ Program Files / MATLAB / R2015aISE C
：/Xilinx/14.7/ISE_DS/ISE -----------------------------------------
---------------------------------------错误摘要：错误0001：致命内部错误阻止
：'I06_vol13_DITC_sensorless_2016_04_06_loader_ver / Implementation_FPGA / transform_input_values / Master_enable'----------------------------------------
----------------------------------------错误0001：报告人：'I06_vol13_DITC_sensorless_2016_04_06_loader_ver / Implementation_FPGA
/ transform_input_values / Master_enable'Details：Xilinx Blockset Library中发生内部错误。请尽可能详细地将此错误报告给Xilinx（http://support.xilinx.com）。
您也可以在http：//support.xilinx.com上找到Answers数据库和其他在线资源的即时帮助。由于您的设计中可能出现此处内部错误导致的未使用错误，我们建议您仔细检查
阻止报告内部错误。
Iferrors仍然存在，我们建议您重新启动MATLAB .----------------------------------------
----------------------------------------
我已经检查了一些旧版本的实现，但旧版本给我同样的错误。
我该如何解决这个错误？
提前致谢



以下为原文

Hi all,

when I start to generate the vhdl code in system generator than I get this message:

Begin generation
Checking model status
Checking simulation times
Performing compilation and generation

*** ERROR ***

Errors occurred during netlist generation.
Error reported by S-function 'sysgen' in 'I06_vol13_DITC_sensorless_2016_04_06_loader_ver/Implementation_FPGA/transform_input_values/Register35':
A summary of Sysgen errors has been written to C:/Users/Dima/Desktop/Studium/Matlab Projekte/aktuell/Changing_Force_Table/I06_vol13_DITC_sensorless_2016_04_06_loader_ver_sysgen_error.log

-----------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------- Version Log ----------------------------------
Version                                 Path
System Generator                        C:/Xilinx/14.7/ISE_DS/ISE/sysgen
Matlab 8.5.0.197613 (R2015a)            C:/Program Files/MATLAB/R2015a
ISE                                     C:/Xilinx/14.7/ISE_DS/ISE
--------------------------------------------------------------------------------
Summary of Errors:
Error 0001: Fatal Internal Error
     Block: 'I06_vol13_DITC_sensorless_2016_04_06_loader_ver/Implementation_FPGA/transform_input_values/Master_enable'
--------------------------------------------------------------------------------

Error 0001:

Reported by:
  'I06_vol13_DITC_sensorless_2016_04_06_loader_ver/Implementation_FPGA/transform_input_values/Master_enable'

Details:
An internal error occurred in the Xilinx Blockset Library.

Please report this error to Xilinx (http://support.xilinx.com),
in as much detail as possible. You may also find immediate help
in the Answers Database and other online resources at http://support.xilinx.com.

Since it is possible that this internal error resulted from an
unhandled usage error in your design, we advise you to carefully
check the usage of the block reporting the internal error. If
errors persist, we recommend that you restart MATLAB.
--------------------------------------------------------------------------------

I have check the implementation with some older versions but the older versions give me the same error.
How can I fix this error?

Thanks in advance