如何同步DCM的输出？

戈登，
不，推断DDR设计HDL不会发生，因为设备没有可以映射到的DDR特定基元。
相反，必须手动执行此操作（基元的直接实例化或处理两个时钟的块）。
我不知道你的情况有多容易。
购买38.4 Xtal振荡器可能更简单（也更便宜）。
你需要做多少？
如果这只是一个单元，为了展示一些东西，那么我会在级联中找到两个DFS。
它可能无法在100％的所有部件中使用，但是对于一个演示，它很好......
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

Gordon,
 
No, inferring DDR deign from HDL is not going to happen, as the devices do not have DDR specific primitives that can be mapped to.
 
Rather, one has to do this by hand (direct instantiaition of primitives, or blocks to handle the two clocks).
 
I do not know how easy this is to do in your case.  Might be simpler (and cheaper) to buy a 38.4 Xtal oscillator.
 
How many do you need to make?
 
If this is just one unit, to demonstrate something, then I would palce two DFS in cascade.  It might not work in 100% of all parts, over all time, but for one demo, it is just fine...
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

戈登，
您无法同步DCM。
但是，我认为你可以从一个DCM中获取所有内容。
所有输出都可以在一个DCM中使用，因此我将使用CLK2X，而不是用于38.4的CLKFX，以及用于19.2的CLK0。
现在，重置后，一个DCM的关系始终相同。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Gordon,

You can not synchronize DCM's.  But, I think you can get everything out of one DCM.
 
All outputs can be used from the one DCM, so I would use the CLK2X, not the CLKFX for the 38.4, and a CLK0 for the 19.2.  Now the relationship is always the same, after a reset, from one DCM.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

嗨奥斯汀，
感谢您的回复。
外部晶体为50MHz，即CLKIN。
所以我认为CLK0不能设置为19.2MHz，对吗？
戈登



以下为原文

Hi Austin,
 
Thanks for your reply.
 
The external crystal is 50MHz, that is CLKIN.  So I think CLK0 can't be set to 19.2MHz, right?
 
Gordon

Grodon，
不。
从50获得19.2需要更多的工作。
分数合成，DDFS，东西。
我不认为一个DCM中的M / D可以使用2到32之间的值来执行此操作。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Grodon,

Nope.  Getting 19.2 from 50 requires a bit more work.  Fractional synthesis, DDFS, something.  I don't think M/D in one DCM can do this with values from 2 to 32.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

我可以通过使用来自ip核心生成器的“与两个DCM SP v9.1i串联级联”来创建19.2MHz时钟。
我也需要38.4MHz，但由于可能存在抖动问题，我不想将19.2MHz输出时钟级联到另一个DCM。
或者这会是一个问题吗？
还有其他方法吗？



以下为原文

I was able create the 19.2MHz clock by using the "Cascading in series with two DCM SP v9.1i" from the ip core generator.
 
I need the 38.4MHz as well, but I don't want to cascade the 19.2MHz output clock to another DCM because of the possible jitter issue.  Or will that be an issue?
 
Any other solution?

戈登，
那么合成38.4呢？
然后一个简单的除以2（一个CLB DF）可能足以让你获得19.2 MHz，或者使用DFF为每个其他38.4时钟提供时钟使能并运行38.4时钟上的所有内容......
级联中的M和D值是做什么的？
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Gordon,
 
What about synthsizing 38.4 instead?  Then a simple divide by two ( a CLB DF) might be sufficent to get you 19.2 MHz, or use the DFF to provide a clock enable for every other 38.4 clock and run everything on the 38.4 clock...
 
What are the M and D values in a cascade to do this?
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

奥斯汀，
我不确定我是否能产生38.4MHz的输出。
但即使我可以，使用DFF来获得19.2MHz会因DFF的延迟而产生小的相移，对吧？
我获得19.2MHz时钟的方法是使用“具有两个DCM SP v9.1的串联级联”IP内核。
在IP内核生成器应用程序中，对于DCM_SP INST1，我在“选择用于级联的时钟：”下拉列表中选择了“CLKDV”。
在“INST1的常规设置”页面中，我在“按值划分”下拉列表中选择了“2.5”。
然后对于DCM_SP INST2，我设置M = 24和D = 25.并且CLKFX将变为19.2MHz。
戈登



以下为原文

Austin,
 
I am not sure if I could generate a 38.4MHz output.  But even if I could, using DFF to get the 19.2MHz would produce a small phase shift due to the delay of the DFF, right?
 
The way that I get the 19.2MHz clock is to use the "Cascading in Series with Two DCM SP v9.1" IP core.
In the IP core generator application, for DCM_SP INST1, I selected "CLKDV" in the "Select clock to be used for cascading:" drop down list.
In the "General Setup for INST1" page, I selected "2.5" in the "Divide by Value" drop down list.
Then for the DCM_SP INST2, I set M=24 and D = 25.  And the CLKFX will become 19.2MHz.
 
Gordon
 

戈登，
好吧，这很酷，因为除以2.5是一个非显而易见的步骤，允许您只使用一个DFS跟随。
125/96是获得38.4所需的分数M / D，而且仅使用一个DFS阶段就不能轻易完成。
两个可以工作，（25 / 12,5 / 8），但这是两个DFS的级联，不推荐。
它可能会起作用，但我们不保证它（因为我们无法测试级联中两个DCMS的每种可能组合）。
如何在上升沿和下降沿使用19.2？
实际上，您正在使用19.2 MHz进行DDR（双倍数据速率）？
这样你仍然有一个时钟域，你还可以在另一个BUFG时钟树中使用CLKFX180时钟来获得“其他”相位，以获得有效的38.4 MHz数据速率......甚至CLKFX上的时钟和CLKFX180上的奇数时钟。
..
你需要在38.4“发送”数据吗？
如果接收端能够“接受”它作为输入，你可以以19.2 DDR（19.2时钟）发送它。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Gordon,
 
OK, that is cool, as the divide by 2.5 is a non-obvious step that allows you to use only one DFS following.
 
125/96 is the fractional M/D required to get 38.4, and this is not done so easily with only one DFS stage.  Two would work, (25/12, 5/8) but that is a cascade of two DFS that is not recommended.  It will probably work, but we don't guarantee it (as we can not test every possible combination of two DCMS in cascade).
 
What about using the 19.2 on both rising, and falling edges?  In effect, you are doing DDR (double data rate) with 19.2 MHz?  This way you still have one clock domain, and you also use the CLKFX180  clock in another BUFG clock tree to get the "other" phase to get the effective 38.4 MHz data rate ... even clocks on CLKFX, and odd clocks on CLKFX180 ...
 
Do you need to "send" data out at 38.4?  You could send it at 19.2 DDR (with the 19.2 clock) if the receiving end can "take" this as an input.
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

奥斯汀，
这听起来像个好计划。
但Spartan 3A是否支持“总是@（posedge clk或negedge clk）”？
或“总是@（posedge clk或posedge clk180）”？
戈登



以下为原文

Austin, 
 
This sounds like a good plan.  But does Spartan 3A support "always @( posedge clk or negedge clk)"? or "always @( posedge clk or posedge clk180)"?
 
Gordon

戈登，
不，推断DDR设计HDL不会发生，因为设备没有可以映射到的DDR特定基元。
相反，必须手动执行此操作（基元的直接实例化或处理两个时钟的块）。
我不知道你的情况有多容易。
购买38.4 Xtal振荡器可能更简单（也更便宜）。
你需要做多少？
如果这只是一个单元，为了展示一些东西，那么我会在级联中找到两个DFS。
它可能无法在100％的所有部件中使用，但是对于一个演示，它很好......
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Gordon,
 
No, inferring DDR deign from HDL is not going to happen, as the devices do not have DDR specific primitives that can be mapped to.
 
Rather, one has to do this by hand (direct instantiaition of primitives, or blocks to handle the two clocks).
 
I do not know how easy this is to do in your case.  Might be simpler (and cheaper) to buy a 38.4 Xtal oscillator.
 
How many do you need to make?
 
If this is just one unit, to demonstrate something, then I would palce two DFS in cascade.  It might not work in 100% of all parts, over all time, but for one demo, it is just fine...
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose