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我正在使用ISE Webpack v14.7。
我不时实现我的VHDL设计(针对Spartan6 FPGA),我发现我没有实现时序收敛。 然后我做的是使用SmartXplorer。 执行此操作并找到有效的策略后,我选中该策略旁边的框,然后单击“复制结果”。 在这种情况下还有待完成的只是“生成编程文件”。 但是,有一些迹象表明SmartXplorer并没有完成通常所做的所有事情,例如“设计概述”下的“timing Constaints”选项显示为灰色,所以我所做的就是选择“Rerun All”on “生成编程文件”上的右键菜单。 我在这里期望的是,SmartXplorer发现的策略设置现在已被复制,因此每次重建时都应该得到完全相同的结果。 我的期望是错的吗? 它大部分时间似乎以这种方式工作,但我也有一些情况,它一直没有。 SmartXplorer表示所有约束都已通过,但是当我复制结果并重建它时,它会在某些约束条件下失败。 以上来自于谷歌翻译 以下为原文 I'm using ISE Webpack v14.7. From time to time when I implement my VHDL designs (targeting Spartan6 FPGAs) I find that I don't achieve timing closure. What I then do is to use SmartXplorer. After doing this, and finding a strategy that works, I check the box next to that strategy and click "Copy Results". What remains to be done in this situation is just to "Generate Programming File". However, there are some indications that SmartXplorer didn't do all the things that are normally done, for instance the "Timing Constaints" option under "Design Overview" is grayed out, so what I do is instead to choose "Rerun All" on the right-click menu on "Generate Programming File". What I expect here is that the strategy settings found by SmartXplorer have now been copied, so I should get exactly the same result every time I rebuild it all. Is my expectation wrong? Most of the time it seems to work this way, but I also have cases where it consistently doesn't. SmartXplorer says that all constraints passed, but when I copy the results and rebuild it all it fails on some constraint. |
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2个回答
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你好Cblixt,
您的期望是正确的,使用相同的网表和相同的软件选项,结果应该是相同的。 我看到一些客户的设计在网表中有轻微的变化,导致结果不同。 谢谢,克里斯 以上来自于谷歌翻译 以下为原文 Hello Cblixt, Your expectations are correct, that with the same netlist, and same software options, the results should be the same. I have seen some customer's design that has a minor change in the netlist, which causes the results to be different. Thanks, Chris |
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嗨克里斯,
那么在所有情况下它似乎都不符合我的期望。 我现在有一个设计,当我第一次清理它的项目文件然后执行“重新运行全部”时,在我的一个时序约束中出现了0.188 ns的设置违规。 当我在此运行SmartXplorer时,它已经在MapRunTime策略中传递,如下所示: 这让我感到很惊讶,因为我认为这是默认使用的策略。 无论如何,我选中此结果的复选框,然后单击“复制结果”。 如果我然后右键单击“生成编程文件”并选择“重新运行全部”,它再次出现一次设置违规0.188 ns和时序分数188。 我意识到这意味着我也在重新合成设计,但如果设置相同,网表应该是相同的(设计当然不会改变)。 如果我,而不是重新运行所有,只需重新运行Place& 路由步骤然后生成编程文件,我最终得到一个明显的时序清洁设计。 所以基本上,这对我来说不是一个大问题,只要我能确定它实际上在最后说出来的时候通过所有约束。 你会说那是这样的吗? 问候, 基督教 以上来自于谷歌翻译 以下为原文 Hi Chris, Well it does not seem to work according to my expectations in all cases. I have a design right now, that when I first clean up its project files and then do "Rerun All" comes out with a setup violation of 0.188 ns in one of my timing constraints. When I run SmartXplorer on this, it passes already on the MapRunTime strategy, like so: This surprises me a bit, because I would have thought that was the strategy used by default. Anyway, I check the box for this result and click "Copy Results". If I then just right-click "Generate Programming File" and select "Rerun All", it again comes out with a single setup violation of 0.188 ns and a timing score of 188. I realize that this means I'm also re-synthesizing the design, but the netlist should be the same if the settings are the same (the design is of course unaltered). If I, instead of rerunning all, just rerun the Place & Route step and then generate programming file, I end up with an apparently timing clean design. So basically, this is not a big problem for me as long as I can be sure that it actually passes all constraints when it says so at the end. Would you say that is the case? Regards, Christian |
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