在使用Vivado GUI实现和分配引脚信息后xdc约束文件中看不到结果

嗨@ tchin123，
I / O规划可以在各种设计阶段完成，例如从头开始的pre-rtl或导入csv或xdc文件，使用rtl标头，或者在使用网表合成之后（有时设计时钟更有意义）。
您可以在实现后查找XDC文件中放置端口的约束。
您可以将约束写入目标约束文件，如下所示：1。
规划完成后，选择文件>保存约束。
在“源”窗口中，双击约束文件夹constr_.3下的.xdc文件。
请注意写入XDC文件的新物理约束。
您可以在I / O规划上查看本教程。
实验1描述了综合之前的I / O规划过程，然后才能获得具有已定义I / O端口的综合网表或RTL源。虽然实验2我想在综合后描述I / O规划功能。
还提供了IO规划视频概述。
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以下为原文

Hi @tchin123,
 
I/O planning can be done at various design stages like pre-rtl from scratch or import csv or xdc file, with rtl header, or after synthesis with netlist (better at times as design is clock aware). You might look for the constraint of the placed port in the XDC file after implementation.
 
You can write the constraints to the target constraint file as:
1. After your planning, select file > save constraints.
2. In the Sources window, double-click the .xdc file under the constraint folder constr_.
3. Notice the new physical constraints written to the XDC file.
 
You can check this tutorial on I/O planning. The lab 1 describes the I/O planning process prior to synthesis, before you have a synthesized netlist or RTL sources with defined I/O ports. While the lab 2 I guess describes I/O planning capabilities after synthesis. There is also IO planning video overview available.
 
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Vivado在我的Kintex设计中为C4，B6，B2和A4引脚分配了PCIe I / O端口。
我可以在I / O Ports面板中看到它。
我甚至将位文件编程到我的FPGA中并且正在工作但我在任何xdc约束文件中都没有看到它。
这些针节省在哪里？



以下为原文

Vivado assigned the PCIe I/O ports in my Kintex design at pin C4, B6, B2 and A4. I could see it in the I/O Ports panel.
I even programmed the bit file into my FPGA and is working but I do not see it in any of my xdc constraint file. Where are these pins save?
 

使用多个约束文件也很常见，特别是取决于电路板预设，特定IP等。
我已经看过很多次，用户认为.xdc被认为是唯一的 - 当它不是，而其他xdc文件有一些限制......
当然，有时你会“幸运”，这个工具碰巧选择了你真正想要的无约束的物理位置 - 这一次。
尝试在TCL控制台中运行它，以确保您了解所有正在播放的xdc文件 
report_compile_order -constraints
干杯，
BT



以下为原文

It is also not uncommon to have multiple constraint files used, particularly depending on board presets, specific IP, etc.
I've seen quite a few times where the user assumed the .xdc being looked at was the only one - when it wasn't and other xdc files had some of the constraints...
Of course, sometimes you "get lucky" and the tool happened to choose the unconstrained physical locations you actually wanted - this time.
 
Trying running this in the TCL console to make sure you are aware of all of the xdc files actually in play
    report_compile_order -constraints
 
Cheers,
bt