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我买了一块使用ADS42lb69芯片的评估板(FMC164),所提供的示例设计是使用ISE制作的,尚未更新。 此示例导致实现警告,让我尝试首先描述时钟路径: 采样频率为250 MHz ADC提供500 MHz时钟,时序为QDR 250MHz,您可以将其视为500 MHzDDR 他们使用BUFMR对象将此时钟除以2 ISerdes使用快速块和分频时钟 分频时钟将是数据时钟 这就是他们处理和分割这个时钟所做的事情: ibufds_inst:ibufds - 接收LVDS 500 MHz时钟 通用地图( DIFF_TERM =>正, IOSTANDARD =>“LVDS_25” )港口地图( i => adc_clk_p, ib => adc_clk_n, o => adc_clk_pn_in ); bufmr_inst:bufmr 港口地图( i => adc_clk_pn_in, o => adc_clk_pn_in_bfmr ); bufio_inst:bufio 港口地图( i => adc_clk_pn_in_bfmr, o => adc_clk_pn ); adc_clk_pn_inv(iinst)“7SERIES”, BUFR_DIVIDE =>“2” )港口地图( clr =>'0', ce =>'1', i => adc_clk_pn_in_bfmr, o => adc_clk_pn_div ); Iserdes稍后将使用快速(500 MHz)时钟,快速(500 MHz)反相时钟,分频(250 MHz)时钟。 实施提供以下警告: [放置30-809] IBUF实例/clk_receiver_gen[0].ibufds_inst驱动BUFMR实例/clk_receiver_gen[0].bufmr_inst。 这需要将IBUF实例放置在支持多区域时钟(MRCC)的IO站点上,但IBUF锁定到站点IOB_X0Y178,该站点是单区域时钟能力(SRCC)IO站点。 可用于同一IO库的可用MRCC IO站点如下: IOB_X0Y174 IOB_X0Y176 如果需要使用SRCC IO站点,则用户可以在连接IBUF和BUFMR负载的网络(/ lvds_clk_rx / adc_clk_pn_in_0)上应用CLOCK_DEDICATED_ROUTE = FALSE约束以绕过此警告。 我真的不明白这个警告。 使用的当前站点是IOB_X0Y178(由工具设置)。 我的理解是这样的网站布局与公司提供的I / O位置有关,并且在他们制造这个电路板时设置。 这是他们在设计FMC连接时发生的某种错误吗? 如果这是真的,那么我们无能为力,我们能否合理地应用警告中提到的约束来在将来的实现中忽略这个“错误”?谢谢 G.W.,NIST - 时间频率计量 以上来自于谷歌翻译 以下为原文 hello, I bought an evaluation board (FMC164) that uses the ADS42lb69 chip, and the provided example design was made using ISE and has not been updated. This example leads to an implementation warning, let me try to describe the clock path first:
ibufds_inst: ibufds -- Receives LVDS 500 MHz clockgeneric map ( DIFF_TERM => TRUE, IOSTANDARD => "LVDS_25") port map ( i => adc_clk_p, ib => adc_clk_n, o => adc_clk_pn_in);bufmr_inst: bufmrport map ( i => adc_clk_pn_in, o => adc_clk_pn_in_bfmr);bufio_inst: bufioport map ( i => adc_clk_pn_in_bfmr, o => adc_clk_pn);adc_clk_pn_inv(iinst) <= not(adc_clk_pn(iinst));bufr_inst: bufrgeneric map ( SIM_DEVICE => "7SERIES", BUFR_DIVIDE => "2") port map ( clr => '0', ce => '1', i => adc_clk_pn_in_bfmr, o => adc_clk_pn_div);the Iserdes will later use both the fast (500 MHz) clock, the fast (500 MHz) inverted clock, the divided (250MHz) clock. Implementation gives the following warning: [Place 30-809] IBUF instance /clk_receiver_gen[0].ibufds_inst drives BUFMR instance /clk_receiver_gen[0].bufmr_inst. This requires the IBUF instance to be placed on a multi-region clock capable (MRCC) IO site, but the IBUF is locked to site IOB_X0Y178 which is a single-region clock capable (SRCC) IO site. The available MRCC IO sites available for use in the same IO bank are the following:IOB_X0Y174IOB_X0Y176If there is a requirement to use an SRCC IO site, the user can apply the CLOCK_DEDICATED_ROUTE=FALSE constraint on the net (/lvds_clk_rx/adc_clk_pn_in_0) connecting the IBUF and the BUFMR load to bypass this warning.I don't really understand this warning. The current site being used is IOB_X0Y178 (which is set by the tool). My understanding is site placement like these are tied to the I/O placement provided the company and set at the time they manufactured this board. Is this some kind of error they made at the time they designed their FMC connection? If this is true, there's not much we can do, can we reasonable apply the constraint mentioned in the warning to ignore this "error" in future implementations? thank you G.W., NIST - Time Frequency metrology |
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@guillaumebres,
你有可能分享这个项目吗? 如果是,那么我可以发送ftp链接。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @guillaumebres, Is it possible for you to share the project? If yes, then I can send you the ftp link. --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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