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当我实现我的设计时,它会报告警告“没有找到set_false_path约束的有效对象,带有选项'-from [get_clock userclk1]'”。但我可以使用TB“get_clocks userclk1”在打开的综合或实现设计中获取此时钟,
我怎么能解决这个警告? 以上来自于谷歌翻译 以下为原文 When I Implement my design,it reports the warnning "no valid object found for set_false_path constraint with option '-from [get_clock userclk1]'".But I can get this clock in the opened synthesis or implementation design using theTCl "get_clocks userclk1",how can I solve this warnning? |
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我在set_false_path约束中看到了一个拼写错误? 我从[get_clock userclk1]看到。 你能确认一下吗? --hs -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 hi, is there a typo that i see in the set_false_path constraint? I see from [get_clock userclk1]. can you confirm and check? --hs ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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一种可能性是尚未定义时钟。
XDC文件是包含约束命令的脚本。 这些命令在项目流程中的适当时间按照由许多因素确定的顺序进行解析和执行。 set_false_path命令显然必须在创建userclk1的create_clock命令之后完成。 如果这些文件在同一文件中的顺序错误,或者(更有可能)在不同的文件中,则可能在具有create_clock命令的文件之前读取带有set_false_path命令的文件。 这可以解释为什么在尝试set_false_path命令时会收到消息,但是您可以交互执行get_clocks userclk1命令 - 当您在Tcl控制台中拥有控制权时,将加载整个设计,包括执行所有XDC脚本。 当涉及到IP时,事情会变得更加复杂。 如果在XDC文件中为IP定义时钟,则可能在合成时未定义时钟(因为IP在合成时是黑盒子),但稍后定义(约束) 在合成后再次处理)。 那么,请告诉我们create_clock相对于set_false_path的位置。 如果是订单,则可以通过将文件的PROCESSING_ORDER属性设置为EARLY或LATE(而不是NORMAL,这是默认值)来修改XDC处理的顺序。 Avrum 以上来自于谷歌翻译 以下为原文 One possibility is that the clock is not yet defined. XDC files are scripts that contain constraint commands. These commands are parsed and executed at the right time in the project flow in an order determined by a number of factors. The set_false_path command clearly has to be done after the create_clock command that creates userclk1. If these are in the wrong order in the same file, or (more likely) are in different files, then it is possible that the file with the set_false_path command is read before the one with the create_clock command. This would explain why you get a message when the set_false_path command is attempted, but you can execute the get_clocks userclk1 command interactively - when you have control in the Tcl console, the whole design is loaded, including executing all the XDC scripts. Things can get even more complicated when IP are involved. If the clock is defined in the XDC file for an IP, then it is possible that the clock is not defined at the time of synthesis (since the IP is a black box at the time of synthesis), but is defined later on (constraints are processed again after synthesis). So, tell us about where the create_clock is with respect to the set_false_path. If it is an order thing, then the order of XDC processing can be modified by setting the PROCESSING_ORDER property of the file to EARLY or LATE (instead of NORMAL, which is the default). Avrum |
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另一个微不足道的原因可能是,如果您从其他文档中复制粘贴约束等,并且它可能包含某些可能正在正确读取命令的特殊字符。或者尝试从GUI编写Timing约束,因为这应该找到
确切的时钟名称,没有任何错误拼写的时钟名称。 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 One other trivial reason could be if you have copy pasted the constraint from a different document etc and it might have include certain special characters which might be reading the commands incorrectly. Alternately try to write the Timing constraints from the GUI, since this should find the exact clock name without chance of any mis-spelt clock names.Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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