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我已经在Vivado的一个实例上工作了几个小时，突然，在修改单个VHDL文件之后，向导要求刷新设计然后我要求完全重建比特流，我得到以下错误： [DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型为'design_1_i / axi_mem_intercon / s00_couplers / auto_pc / design_1_auto_pc_1'的单元'design_1_i / axi_mem_intercon / s00_couplers / auto_pc'具有未定义的内容，被视为黑匣子。 必须定义此单元格的内容才能使opt_design成功完成。[DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型为'design_1_i / clk_wiz_0 / design_1_clk_wiz_0_0'的单元'design_1_i / clk_wiz_0'具有未定义的内容和 被认为是一个黑盒子。 必须为opt_design定义此单元格的内容才能成功完成。[DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型'design_1_i / proc_sys_reset_0 / design_1_proc_sys_reset_0_0'的单元'design_1_i / proc_sys_reset_0'具有未定义的内容和 被认为是一个黑盒子。 必须定义此单元格的内容才能使opt_design成功完成。[DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型为'design_1_i / processing_system7_0 / design_1_processing_system7_0_0'的单元'design_1_i / processing_system7_0'具有未定义的内容和 被认为是一个黑盒子。 必须为opt_design定义此单元格的内容才能成功完成。[DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型为'design_1_i / ps7_0_axi_periph / s00_couplers /的单元'design_1_i / ps7_0_axi_periph / s00_couplers / auto_pc' auto_pc / design_1_auto_pc_0'具有未定义的内容，被视为黑盒子。 必须定义此单元格的内容才能使opt_design成功完成。[DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型为'design_1_i / rst_ps7_0_133M / design_1_rst_ps7_0_133M_0'的单元'design_1_i / rst_ps7_0_133M'具有未定义的内容和 被认为是一个黑盒子。 必须定义此单元格的内容才能使opt_design成功完成。[DRC 23-20]规则违规（INBB-3）黑匣子实例 - 类型为'design_1_i / xlconstant_0 / design_1_xlconstant_0_1'的单元'design_1_i / xlconstant_0'具有未定义的内容和 被认为是一个黑盒子。 必须为opt_design定义此单元格的内容才能成功完成。 基本上，向导生成的所有块，除了我的VHDL块都是设计中的黑盒子。 真是一个迷人的惊喜，因为我甚至没有重新启动工具，就像那样，在两个构建之间...... （我之前有过这样的问题，但幸运的是它发生在我的VHDL文件中，似乎该工具将设置从“自动构建顺序”修改为“手动”，无论出于何种原因，从不单击它。发现了 解决方案在线并解决了问题。 这次再次检查，但它没有解决问题） 你有什么建议可以轻松解决这个问题吗？ 如果没有，解决问题的途径是什么（最坏的情况是从头开始重新创建整个设计?????（我有数百个电线和至少12个电路板+大约20个IO定义）） 无论如何，我被困住了，不会在这个过夜。 现在是凌晨2:30。 比太阳升起之前更好的睡眠而不是试图修复它... 最好的祝福， 罗曼。 PS：它似乎抱怨许多文件的路径，如 C： Xilinx2 Vivado 2016.4 DATA IP 赛灵思 processing_system7_v5_5 XIT xdc.xit 但我检查了我的硬盘驱动器，文件在那里，没有问题。 （使用文本编辑器检查内容，数据未损坏） 以上来自于谷歌翻译 以下为原文 Hi. I have been working multiple hours on one instance of Vivado and suddenly, after modifying a single VHDL file, wizard ask for refresh of the design and then I asked for a complete rebuild of the bitstream, I got the following errors : [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/axi_mem_intercon/s00_couplers/auto_pc' of type 'design_1_i/axi_mem_intercon/s00_couplers/auto_pc/design_1_auto_pc_1' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/clk_wiz_0' of type 'design_1_i/clk_wiz_0/design_1_clk_wiz_0_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/proc_sys_reset_0' of type 'design_1_i/proc_sys_reset_0/design_1_proc_sys_reset_0_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/processing_system7_0' of type 'design_1_i/processing_system7_0/design_1_processing_system7_0_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc' of type 'design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc/design_1_auto_pc_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/rst_ps7_0_133M' of type 'design_1_i/rst_ps7_0_133M/design_1_rst_ps7_0_133M_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'design_1_i/xlconstant_0' of type 'design_1_i/xlconstant_0/design_1_xlconstant_0_1' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. Basically ALL the block generated by the wizard, except my VHDL blocks are black boxes inside the design. What a chARMing surprise, as I did not even restart the tool, just like that, between two build... (I had previously today an issue like that, but luckily it happend with my VHDL files, and it seems that the tool modified the setup from "Automatic build order" to "Manual" for whatever reason by itself, never clicked it. Found the solution online and fixed the problem. Checked again this time, but it did not fix the problem) Do you have any advice to fix that easily ? If not, what is the route to fix the problem (worst case is to recreate the whole design from scratch again ????? (I have hundreds of wire and at least 12 blocks + around 20 IO defined)) Anyway, I am stuck and wont be spending the night on this. It is 2:30 AM. Better sleep than trying to fix that until the sun comes up... Best regards, Romain. PS : It seems to complain about the path to many files like C:Xilinx2Vivado2016.4dataipxilinxprocessing_system7_v5_5xitxdc.xit But I checked my HDD and the file were there, no issues. (checked the content with a text editor, data was not corrupted) 
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解决了 ：
单击流导航器中[IP Integrator]中的[Generate Block Design]似乎完成了重建两个构建之间工具丢失的信息的工作。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 SOLVED : Click on [Generate Block Design] in [IP Integrator] in flow navigator seems to have done the job of recreating the information that was lost by the tool between two build. View solution in original post |
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解决了 ：
单击流导航器中[IP Integrator]中的[Generate Block Design]似乎完成了重建两个构建之间工具丢失的信息的工作。 以上来自于谷歌翻译 以下为原文 SOLVED : Click on [Generate Block Design] in [IP Integrator] in flow navigator seems to have done the job of recreating the information that was lost by the tool between two build. |
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