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嗨,
在通过批处理模式或命令运行实现时,我的tcl脚本正在执行以下操作: ################################################## #SET DESIGN VARIABLES ########################################################### ###### set DesignName“phif_top”set PartName“XC7V2000TFHG1761-2”link_design -name $ {DesignName} -part $ {PartName} -mode out_of_context #optimize netlist opt_design #Place Design place_design #rebuffer high fanout nets phys_opt_design write_checkpoint -force $ outputDir / post_place report_clock_utilization -file $ outputDir / post_place_clock_util.rpt report_utilization -file $ outputDir / post_place_util.rpt #runtry router,report actual utilization and timing,write checkpoint design,run drc,write verilog和xdc out route_design write_checkpoint -force $ outputDir / post_route report_timing_summary -file $ outputDir / post_route_timing_summary.rpt report_timing -sort_by group -max_paths 100 -path_type summary -file $ outputDir / post_route_timing.rpt report_utilization -file $ outputDir / post_route_util.rpt report_power -file $ outputDir / post_route_power.rpt report_drc -file $ outputDir / post_imp_drc.rpt write_verilog -force $ outputDir / bft_impl_netlist.v write_xdc -no_fixed_only -force $ outputDir / bft_impl.xdc ################################################## ############## 在批处理模式下运行此脚本时,实现了设计的成功完成。 但是如果我在Vivado GUI中打开一个项目,将.edf和.xdc文件作为源文件包含到项目中并运行一个只有下面这些行的tcl脚本,这样设计就是OOC,然后在GUI中运行实现,然后我就是 面临很多错误: ################################################## #SET DESIGN VARIABLES ########################################################### ###### set DesignName“phif_top”set PartName“XC7V2000TFHG1761-2”link_design -name $ {DesignName} -part $ {PartName} -mode out_of_context 错误是例如: [放置30-415]由于过度使用,IO放置失败。 此设计包含1336个I / O端口,而目标设备:7v2000t包:fhg1761,仅包含850个可用用户I / O. 目标器件有850个可用的I / O引脚,其中0个已被用户锁定的I / O占用。要纠正此问题:1。 确保您定位到正确的设备和包。 如有必要,请选择更大的设备或不同的包装。 检查设计的顶级端口,确保指定正确的端口数。 考虑设计更改以减少必要的I / O数量。 放置[30-68]实例IBUF_184(IBUF)未放置。 请让我知道我错在哪里,为什么我无法在Vivado GUI中以OOC模式执行。 感谢你的帮助。 感谢致敬, Amitra 以上来自于谷歌翻译 以下为原文 Hi, While running implementation through batch mode or commands, my tcl script is doing the following: ################################################ ### SET DESIGN VARIABLES ### ################################################# set DesignName "phif_top" set PartName "XC7V2000TFHG1761-2" link_design -name ${DesignName} -part ${PartName} -mode out_of_context # optimize netlist opt_design #Place Design place_design # rebuffer high fanout nets phys_opt_design write_checkpoint -force $outputDir/post_place report_clock_utilization -file $outputDir/post_place_clock_util.rpt report_utilization -file $outputDir/post_place_util.rpt # run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out route_design write_checkpoint -force $outputDir/post_route report_timing_summary -file $outputDir/post_route_timing_summary.rpt report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt report_utilization -file $outputDir/post_route_util.rpt report_power -file $outputDir/post_route_power.rpt report_drc -file $outputDir/post_imp_drc.rpt write_verilog -force $outputDir/bft_impl_netlist.v write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc ################################################################ While running this script in batch mode, implementation completes successfully for the design. But if I open a project in Vivado GUI, include the .edf and .xdc files as source files to the project and run a tcl script with only these below lines so that the design is OOC, then run implementation in GUI, then I am facing many errors : ################################################ ### SET DESIGN VARIABLES ### ################################################# set DesignName "phif_top" set PartName "XC7V2000TFHG1761-2" link_design -name ${DesignName} -part ${PartName} -mode out_of_context The errors are for example: [Place 30-415] IO Placement failed due to overutilization. This design contains 1336 I/O ports while the target device: 7v2000t package: fhg1761, contains only 850 available user I/O. The target device has 850 usable I/O pins of which 0 are already occupied by user-locked I/Os. To rectify this issue: 1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary. 2. Check the top-level ports of the design to ensure the correct number of ports are specified. 3. Consider design changes to reduce the number of I/Os necessary. Place [30-68] Instance IBUF_184 (IBUF) is not placed. Please let me know where I am wrong, why I am unable to do implementation in OOC mode in Vivado GUI. Appreciate your help. Thanks and regards, Amitra |
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嗨阿米特拉,
官方流程是将网表添加为超出上下文的DCP文件到项目中。 因此,使用-mode out_of_context运行综合,然后在与综合相同的项目中设置实现运行,或者将此DCP添加到网表项目中。 如果您使用的是第三方合成,则首先需要创建一个OOC检查点: read_edif link_design -mode out_of_context write_checkpoint 最好的祝福, 德赖斯 -------------------------------------------------- -------------------------------------------------- ----------------如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向 在帖子旁边。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi Amitra, The official flow is to add the netlist as Out-of-context DCP file to the project. So run synthesis using -mode out_of_context, and then either setup the implementation runs in same project as synthesis, or add this DCP to a netlist project. If you are using 3rd party synthesis you will first need to create an OOC checkpoint:
Best regards, Dries -------------------------------------------------------------------------------------------------------------------- Please mark the Answer as "Accept as solution" if the information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post. View solution in original post |
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嗨,
您是否在vivado中创建了后期综合项目(用于GUI模式)? 如果没有尝试创建一个后期综合项目,因为顶级是EDIF文件。 在综合设置中,在更多选项字段中写入-mode out_of _context并运行合成,然后执行。 使用GUI时,无需从TCL单独运行link_design。 检查以上是否有效。 问候, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi, Did you create post synthesis project in vivado (for GUI mode)? If not try creating a post synthesis project as the top level is EDIF file. In synthesis settings write -mode out_of _context in the more options field and run synthesis followed by Implementation. There is no need of running link_design seperately from TCL when using GUI. Check if the above works. Regards, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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嗨Deepika,
我已经将项目创建为Post Synthesis项目。 问题是你在快照中显示的,我没有看到任何设置,我可以给出选项“-mode out_of_context”。 是因为已经执行了合成并且已经生成了edf? 我不确定。 在我的项目设置中,我可以看到左侧面板上的所有按钮,“合成”和“IP”除外。 感谢致敬, Amitra 以上来自于谷歌翻译 以下为原文 Hi Deepika, I have created the project as Post Synthesis project. The problem is as you showed in your snapshot, I am not seeing any settings for Synthesis where I can give the option "-mode out_of_context". Is it because synthesis is already performed and edf is already generated? I am not sure. In my Project Settings I can see all the buttons on the left panel except "Synthesis" and "IP". Thanks and regards, Amitra |
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嗨阿米特拉,
官方流程是将网表添加为超出上下文的DCP文件到项目中。 因此,使用-mode out_of_context运行综合,然后在与综合相同的项目中设置实现运行,或者将此DCP添加到网表项目中。 如果您使用的是第三方合成,则首先需要创建一个OOC检查点: read_edif link_design -mode out_of_context write_checkpoint 最好的祝福, 德赖斯 -------------------------------------------------- -------------------------------------------------- ----------------如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向 在帖子旁边。 以上来自于谷歌翻译 以下为原文 Hi Amitra, The official flow is to add the netlist as Out-of-context DCP file to the project. So run synthesis using -mode out_of_context, and then either setup the implementation runs in same project as synthesis, or add this DCP to a netlist project. If you are using 3rd party synthesis you will first need to create an OOC checkpoint:
Best regards, Dries -------------------------------------------------------------------------------------------------------------------- Please mark the Answer as "Accept as solution" if the information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post. |
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嗨,Dries,
由于我使用的是第三方生成的edf网表,因此您的解决方案有效。 以前,我没有阅读edf文件并创建写检查点。 在将它们与link_design命令和运行实现一起包含在脚本中之后,我可以完成实现而不会出错。 谢谢。 问候, Amitra 以上来自于谷歌翻译 以下为原文 Hi Dries, Since I am using a third party generated edf netlist therefore, your solution worked. Previously, I was not reading the edf file and creating write checkpoints. After including them in the script along with link_design command and running implementation, I could complete the implementation without errors. Thank you. Regards, Amitra |
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