为spartan6 XA6SLX75配置SPI闪存编程总是失败

添加限流电阻???
串联端接电阻用于匹配电路板走线的阻抗，以避免振铃并控制不需要的反射。
这不是目前的限制。
33欧姆是一个很好的价值。
如果您继续进行电路板设计和开发工作，您需要学习传输线原理，概念和实践。
这种指导的最佳来源是经验丰富的电路板设计师。
我第一次学习传输线原理的书是William R Blood的MECL系统设计手册。
本书已绝版，但可以购买使用过的副本。 
我已经注意到了QE位，但我没有将PROM的status_reg [9]的QE位设置为1.我不知道怎么做。在iMPACT 13.4软件中。
你能告诉我详细的过程吗？
右键单击Generate Programming File，在弹出菜单中选择Process Properties。
选择Configuration Options，然后设置SPI Configuration Bus Width选项。
您需要重新生成位文件并重新编程SPI闪存。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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在原帖中查看解决方案



以下为原文

Add a current-limiting resistance???
 
A series termination resistor serves to match impedance to the circuit board trace to avoid ringing and control undesired reflections.  It is not a current limit.  33-ohms is a good value.
 
If you continue with board design and development work, you need to learn transmission line principles, concepts, and practices.  The best source of such instruction is an experienced board designer.  The book from which I first learned transmission line principles is the MECL System Design Handbook, by William R Blood.  This book is out of print, but used copies are available for purchase.
 
I have paid attention to the QE bit,  but I do not set the QE bit of the PROM’s status_reg[9] to 1. I do not know how to do it.in iMPACT 13.4 software. Can you tell me detailed process?
 
Right-click on Generate Programming File, select Process Properties in pop-up menu.

 
Select Configuration Options, and set the SPI Configuration Bus Width option.


 
You will need to re-generate the bitfile and re-program the SPI flash memory.
 
-- Bob Elkind

SIGNATURE:
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补充：我离开了CFS和VBATTunconnected。



以下为原文

Supplement :I leave  the CFS and VBATT unconnected.

FPGA_CLK信号没有终止（来自FPGA的CCLK输出）。
这可能是个问题。
如果您修改电路板设计，则应在FPGA附近（引脚Y21）为此信号添加一个33欧姆串联终端电阻。
FPGA是否可靠地配置JTAG？
你能从JTAG可靠地编程W25Q闪存（例如使用iMPACT进行间接编程）吗？
来自UG380图2-13：
图2-13中所示的连接使用Winbond W25Q SPI系列闪存PROM。
要启用Quad输出操作，用户必须将PROM的status_reg [9]的QE位设置为1才能使器件能够以四输出模式进行发送，这在iMPACT软件的编程时完成。
CCLK可以由FPGA或外部时钟源提供。
PROGRAM_B，INIT_B和M0引脚上有默认上拉电阻。
x4的软件支持需要在BitGen中启用x4功能。
SPI器件需要使用特定的寄存器设置进行编程，可以在iMPACT软件中完成，以启用x4输出。
从UG380 v2.3，第43页：
Spartan-6 FPGA中的主SPI配置模式支持Winbond W25Q Quad I / O SPI闪存双（x2）和四位（x4）存储器读命令。
要在软件中启用此配置方法，BitGen spi_buswidth选项用于为SPI x2或x4创建.bit文件。
FPGA最初仍然以x1模式启动，然后切换到x2或x4模式。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

There is no termination on the FPGA_CLK signal (CCLK output from the FPGA).  This might be a problem.  If you revise the board design, you should add a 33-ohm series termination resistor for this signal, near the FPGA (pin Y21).
 

• Does the FPGA configure reliably from JTAG?
  
• Can you reliably program the W25Q flash memory from JTAG (e.g. indirect programming using iMPACT) ?
  

From UG380 Figure 2-13:
 

• The connection shown in Figure 2-13 uses the Winbond W25Q SPI series flash PROM. To enable the Quad output operation, the user must set the QE bit of the PROM’s status_reg[9] to 1 before the device can transmit in quad output mode, which is done at programming time in iMPACT software.
  
• CCLK can be provided by the FPGA or an external clock source.
  
• There are default pull-ups on the PROGRAM_B, INIT_B, and M0 pin.
  
• Software support for x4 requires the x4 capability enabled in BitGen.
  
• The SPI device needs to be programmed with a specific register setting, which can be done in iMPACT software, to enable x4 output.
  

From UG380 v2.3, page 43:
 
The Master SPI configuration mode in Spartan-6 FPGAs supports the Winbond W25Q Quad I/O SPI flash memory dual (x2) and quad bit (x4) memory read commands. To enable this configuration method in software, the BitGen spi_buswidth option is used to create a .bit file for SPI x2 or x4. The FPGA still initially boots in x1 mode and then switches to x2 or x4 mode.
 
 -- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我确信Iconfigure可以从JTAG中可靠地从JTAG whithindirect编程中编程W25Q闪存。
今天我更改了CCLK连接，如下所示： 
但这无济于事。 
根据youradvice，CCLK连接是否像这样修改？ 
添加限流电阻??? 
我已经注意到了QE位，但我没有将PROM的status_reg [9]的QE位设置为1.我不知道怎么做。在iMPACT 13.4软件中。
你能告诉我详细的过程吗？
非常感谢。



以下为原文

      I am sure that I configure reliably from JTAG and program the W25Q flash memory from JTAG whith indirect programming.  Today I changed the CCLK connection, as follow:


  But It was to no avail.
   According to your advice, Is the CCLK connection revised like this?
     
Add a current-limiting resistance???
    I have paid attention to the QE bit,  but I do not set the QE bit of the PROM’s status_reg[9] to 1. I do not know how to do it.in iMPACT 13.4 software. Can you tell me detailed process? 
Thanks very much.

添加限流电阻???
串联端接电阻用于匹配电路板走线的阻抗，以避免振铃并控制不需要的反射。
这不是目前的限制。
33欧姆是一个很好的价值。
如果您继续进行电路板设计和开发工作，您需要学习传输线原理，概念和实践。
这种指导的最佳来源是经验丰富的电路板设计师。
我第一次学习传输线原理的书是William R Blood的MECL系统设计手册。
本书已绝版，但可以购买使用过的副本。 
我已经注意到了QE位，但我没有将PROM的status_reg [9]的QE位设置为1.我不知道怎么做。在iMPACT 13.4软件中。
你能告诉我详细的过程吗？
右键单击Generate Programming File，在弹出菜单中选择Process Properties。
选择Configuration Options，然后设置SPI Configuration Bus Width选项。
您需要重新生成位文件并重新编程SPI闪存。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Add a current-limiting resistance???
 
A series termination resistor serves to match impedance to the circuit board trace to avoid ringing and control undesired reflections.  It is not a current limit.  33-ohms is a good value.
 
If you continue with board design and development work, you need to learn transmission line principles, concepts, and practices.  The best source of such instruction is an experienced board designer.  The book from which I first learned transmission line principles is the MECL System Design Handbook, by William R Blood.  This book is out of print, but used copies are available for purchase.
 
I have paid attention to the QE bit,  but I do not set the QE bit of the PROM’s status_reg[9] to 1. I do not know how to do it.in iMPACT 13.4 software. Can you tell me detailed process?
 
Right-click on Generate Programming File, select Process Properties in pop-up menu.

 
Select Configuration Options, and set the SPI Configuration Bus Width option.


 
You will need to re-generate the bitfile and re-program the SPI flash memory.
 
-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢



以下为原文

Thanks

感谢您的帮助，现在我可以成功配置它。
但是斯巴达人的移民时间太长了。
配置需要956秒。
我的代码只是实现一个端口接收信号而另一个端口输出此信号。 
我想知道影响时间的因素。
谢谢。 
在配置过程中，平台电缆USB II配置时钟（TCK_CCLK_SCK）频率设置为12MHz，移植速率为4Mbit / s。



以下为原文

        Thank you for your help, Now I can configrate it successfully. But The time is too long for spartan6 configration. it takes 956 sec to configrate. My code is only to  implement that one port receive a signal and other one output this signal. 
      I want to know  what factors are influence the time. thanks.  
     The Platform Cable USB II configuration clock (TCK_CCLK_SCK) frequency is  set 12MHz and  configration rate is 4Mbit/s during the configration.

请澄清：
什么操作或过程在956秒内完成？
你如何衡量这个过程的经过时间？
您使用启动选项的BitGen设置是什么？
您使用什么BitGen配置选项？
您使用什么BitGen设置进行常规选项？
您使用什么BitGen设置加密选项？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Please clarify:

• What operation or process completes in 956 seconds?
  
• How are you measuring the elapsed time of this process?
  
• What BitGen setting are you using for Startup Options?
  
• What BitGen setting are you using for Configuration Options?
  
• What BitGen setting are you using for General Options?
  
• What BitGen setting are you using for Encryption Options?
  

-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

1.该过程包括擦除，编程和验证spi flashW25Q64B。
2.一般选项： 
启用：运行设计规则检查器（DRC） 
创建位文件 
启用循环冗余校验（CRC）
3.一般选择： 
移民率为16Mbit / s 
Spi总线宽度为4 
其他人保持默认
4.启动选项 
StartUpClk：CCLK 
其他人保持默认
5.加密选项： 
我不用这个。



以下为原文

1. the process include erasing, programming and verifying the spi flash W25Q64B.
2. General Options : 
     Enable: Run Design Rules Checker (DRC)
    Create Bit File
     Enable Cyclic Redundancy Checking (CRC)
3. General Options:
     Configration Rate is 16Mbit/s
     Spi buswidth is 4
    Others keep default
4.Startup Options
    StartUpClk: CCLK
    Others keep default
5. Encryption Options:
     I do not use it.
   
    

1.该过程包括擦除，编程和验证spi flashW25Q64B。
您描述的是iMPACT / JTAG编程（和间接编程）操作，而不是自我配置。
大多数（也可能全部）BitGen设置不会影响闪存编程时间。
是的，这是缓慢而乏味的。
好消息是您只在开发和调试期间使用这些功能。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

1. the process include erasing, programming and verifying the spi flash W25Q64B.
 
What you describe are iMPACT/JTAG programming (and indirect programming) operations, not self-configuration.  Most (and maybe all) the BitGen settings will not affect the flash memory programming time.
 
Yes, it is slow and tedious.  The good news is that you use these function only during development and debugging.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢，我明白了。



以下为原文

Thank you, I get it.

在spi编程模式下，您可以使用cclk的user_cclk，例如avnet在其spartan6演示版本中使用此方法，它说“Spartan-6 LX75T开发板使用板载Numonyx多位（x4）SPI闪存器件，部分
编号N25Q128A13BSE40F，使用主串行/ SPI配置模式快速配置FPGA。配置FPGA时，闪存时钟由FPGA CCLK引脚提供。为加快PCI Express应用的配置时间，连接40 MHz用户时钟
Bank2中的USERCLK输入。如果USERCCLK不用于配置用于PCI Express应用的Spartan-6 FPGA，则在主机PC上电并枚举PCI Express总线时，可能无法在总线上识别该板。
你可以在avnet网站找到avaluation borad的schmatic



以下为原文

in spi programing mode you can use user_cclk insted of cclk for example avnet use this method in its spartan6 demo borad , and it say "The Spartan-6 LX75T development board utilizes on-board Numonyx multi-bit (x4) SPI flash device, part number N25Q128A13BSE40F, to configure the FPGA quickly using the Master Serial / SPI configuration mode. When configuring the FPGA, the flash clock is sourced by the FPGA CCLK pin. To speed up configuration times for PCI Express applications a 40 MHz User Clock is connected to the USERCLK input in Bank 2. If the USERCCLK is not used to configure the Spartan-6 FPGA for PCI Express applications the board might not be recognized on the bus at the time the host PC powers up and enumerates the PCI Express bus."
 
you can  find  schmatic of ths avaluation borad in avnet site