映射错误RAMB36E1

你能试试最新版本吗？
这似乎是一个错误，因为代码是由FIFO生成器生成的，理想情况下，合成器应该关联RAMB的正确属性。
作为7系列，有​​可能在Vivado尝试这个吗？
问候
Sikta
在原帖中查看解决方案



以下为原文

Can you try in the latest version? This seems a bug as the code is generated by FIFO generator and ideally the synthesizer should associate correct attributes for RAMBs.
 
As its a 7 series, Is it possible to try this in Vivado?
 
Regards
Sikta
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嗨，请查看此AR http://www.xilinx.com/support/answers/45761.html
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
Please check this AR http://www.xilinx.com/support/answers/45761.htmlThanks,Vijay
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你链接的相同答案记录谈到了“寄存器排序”这是一个Map选项。
如果您怀疑问题在合成后出现问题，您可能会尝试将其关闭。
如果在BitGen之前没有实际发现错误，那么可以选择在FPGA编辑器中打开设计，以查看是否可以手动修复BRAM地址连接的问题。
-  Gabor



以下为原文

The same answer record you linked talks about "register ordering" which is a Map option.  You might try to turn that off if you suspect that the problem creeps up after synthesis.
 
If you don't actually hit the error until BitGen, then one option is to open the design in FPGA editor to see if the issue with the BRAM address connection can be fixed manually.
-- Gabor

你能试试最新版本吗？
这似乎是一个错误，因为代码是由FIFO生成器生成的，理想情况下，合成器应该关联RAMB的正确属性。
作为7系列，有​​可能在Vivado尝试这个吗？
问候
Sikta



以下为原文

Can you try in the latest version? This seems a bug as the code is generated by FIFO generator and ideally the synthesizer should associate correct attributes for RAMBs.
 
As its a 7 series, Is it possible to try this in Vivado?
 
Regards
Sikta

各位大家好，谢谢你回答我！实际上我在面对这个问题时，MAP流程正在用planahead运行，正如Gabor告诉我的那样，我试图关闭“注册排序”地图选项，但它没有解决问题
。
然后，我和Sivta建议的Vivado一起尝试了。
这次我使用了Vivado合成器，合成和实现都很好！
我不知道为什么。
有人对此有任何暗示吗？
这是XST或PlanAhead与7系列的错误吗？问候，Aymeric



以下为原文

Hi everybody, and thanks for answering me !

Actually I faced this issue while the MAP process was running with planahead, and as Gabor told me, I tried to turn off the " register ordering" map option, but it did not work out the problem.

Then, I tried it with Vivado as Sikta suggested. This time I used the Vivado synthesizer, and the synthesis and implementation were fine !

I don't know why. Does anybody have any hint on this ? Is that a bug with XST or PlanAhead with 7 series ?

Regards,
Aymeric

从您的结果来看，这似乎是XST的一个错误。
如果您有兴趣，我可以考虑一个实验，您可以在其中使用xst ngc并创建Vivado项目并进行检查。
:)这可能会提供更多信息。
问候
Sikta



以下为原文

From your results, this seems a bug with XST. If you are interested , I can think of a experiment where you could take the xst ngc and create a Vivado project and check. :) That might give some more information.
 
Regards
Sikta

问题是，由于我正在进行部分重新配置，我需要使用PlanAhead14.4来完成。
我尝试与Synplify Pro合成，我在MAP过程中遇到了同样的问题。
只有当我使用Vivado合成器时，设计才能完全实现。我会尝试你的建议，我会告诉你的事。听听，Aymeric



以下为原文

The thing is, since I'm working on partial reconfiguration, I need to do it using PlanAhead14.4.

I tried to synthesize with Synplify Pro, and I got the same issue during the MAP process. The design can be fully implemented only when I use the Vivado synthesizer. 

I'm gonna try what you suggest, and I'll let you know.

Regards,
Aymeric
 

实际上，事实证明Coregen生成的文件是问题所在。
所以我用新的项目设置重新生成它，现在它很好！
感谢您的帮助，问候，Aymeric



以下为原文

Actually, it turns out that the Coregen generated file was the problem. So I regenerated it with new Project Settings and now it's fine !

Thanks for helping,

Regards,
Aymeric

嗨Aymeric，
感谢您的更新。
这对其他用户非常有帮助。
问候
Sikta



以下为原文

Hi Aymeric,
Thanks for your update. That will be really helpful for other users.
 
Regards
Sikta

我只是想花点时间来讨论这个问题。
我在我的一个项目上遇到了同样的错误，这无疑是一个非常紧张的错误。
真的没有办法弄清楚bug在哪里没有蛮力尝试所有想到的小东西，从来不知道你是否真的会得到它。
所以希望我的经验会帮助别人。
在我的情况下，我正在使用Synplify合成SystemVerilog模块（因为ISE不支持SV，是的，我知道Vivado现在做了），然后在翻译阶段将其拉入主要的ISE项目（使用XST合成）
使用“-sd”参数。
一旦ISE到达地图阶段，它就会报告与我的SV模块中使用Synplify合成的一个存储器完全相同的DRC错误。
我在ISE和Synplify中尝试了各种不同的合成，地图选项，没有任何修复它。
然后我想到了安装更新版本的synplify并用它重新合成SV模块并得到一个新的网表。
使用新版本的Synplify重建SV模块修复了DRC错误。
如果有任何帮助，我使用的特定Synplify版本是：
H201303  - 导致Map DRC错误
I2013091  - 修复了Map DRC错误
我想为什么升级synplify修复错误是因为7系列设备在2013年仍然是新的，因此6个月（即2013-03至2013-09）的开发可能允许Synopsys修复一堆错误并获得
关于7系列的综合结果的更多用户反馈。
只是一个理论。
无论如何，希望这有助于某人。
这是一个非常讨厌的问题。
另外，我的目标是XC7A200T。
- 乔纳森



以下为原文

I just wanted to take the time to chime in on this. I ran into this same error on one of my projects and it's admittedly a pretty stressful error. There is really no way to figure out where the bug is without brute force trying everything little thing that comes to mind and never knowing if you'll ever actually get it fixed. So hopefully my experience will help someone else.
 
In my case I was synthesizing a SystemVerilog module with Synplify (because ISE doesn't support SV, and, yes, I know Vivado does now) and then pulling it into the main ISE project (which was syntheized with XST) during the translate phase using the "-sd" argument.  Once ISE got to the map stage it reported the exact same DRC errors with one of the memories in my SV module that had been synthesized with Synplify.  I tried all kinds of different synthesis, map options in both ISE and Synplify and nothing was fixing it. I then got the idea to install a newer version of synplify and resynthesize the SV module with it and get a new netlist.  Rebuilding the SV module with the new version of Synplify fixed the DRC errors.  If it's any help the specific Synplify versions I was using were:
 
H201303 - caused Map DRC errors
I2013091 - fixed Map DRC errors
 
My thought on why upgrading synplify fixed the error is because the 7-series devices were still pretty new back in 2013 and so 6 months (i.e. 2013-03 to 2013-09) of development probably allowed Synopsys to fix a bunch of bugs and get a lot more user feedback on synthesis results for 7-series.  Just a theory.  In any case, hope this helps someone. This is a pretty nasty issue to run into.
 
Also, I was targetting XC7A200T.
-- Jonathon