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我手动尝试在生成语句中推断BRAM。 但如果我这样做: gen_ramb16_s1_s36:对于i在0到31中生成属性DATA_WIDTH_A:整数; - gen_ramb16_s1_s36 .RAMB16BWE_S36_inst的属性DATA_WIDTH_A:标签为9; - 第317行开始RAMB16BWE_S36_inst:RAMB16BWE_S36通用映射( - [...] INITP_06 => X“00000000000000000000000000000000000000000000000000000000000000”,INITP_07 => X“0000000000000000000000000000000000000000000000000000000000000000”)端口映射(DO => DO_RAM, - 32位数据输出DOP =>打开, - 4位奇偶校验输出ADDR => ADDR_RAM, - 9位地址输入CLK => tcm8230md_sys_clk, - 1位时钟DI => DI_RAM, - 32位数据输入DIP =>( 其他=>'0'), - 4位奇偶校验输入EN =>'1', - 1位RAM使能输入SSR =>'0', - 1位同步置位/复位输入WE => WE_RAM(i) - 4位写使能输入结束生成; 这样做,ISE仍然会抛出以下错误: 错误:HDLParsers:164 - “/home/DFK/FPGA_SVN/lib/CAM_TCM8230MD/trunk/tcm8230md_i2c_wrapper.vhd”第317行。解析错误,意外POINT,期待COLON 我究竟做错了什么???? 以上来自于谷歌翻译 以下为原文 Hello! I'm manually trying to infer BRAM in a generate statement. But if I do this: gen_ramb16_s1_s36 : for i in 0 to 31 generate attribute DATA_WIDTH_A : integer; -- attribute DATA_WIDTH_A of gen_ramb16_s1_s36.RAMB16BWE_S36_inst : label is 9; -- Line 317 begin RAMB16BWE_S36_inst : RAMB16BWE_S36 generic map ( -- [...] INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( DO => DO_RAM, -- 32-bit Data Output DOP => open, -- 4-bit parity Output ADDR => ADDR_RAM, -- 9-bit Address Input CLK => tcm8230md_sys_clk, -- 1-bit Clock DI => DI_RAM, -- 32-bit Data Input DIP => (others => '0'), -- 4-bit parity Input EN => '1', -- 1-bit RAM Enable Input SSR => '0', -- 1-bit Synchronous Set/Reset Input WE => WE_RAM(i) -- 4-bit Write Enable Input end generate; Doing so, ISE will still throw out the following error: ERROR:HDLParsers:164 - "/home/DFK/FPGA_SVN/lib/CAM_TCM8230MD/trunk/tcm8230md_i2c_wrapper.vhd" Line 317. parse error, unexpected POINT, expecting COLON what am I doing wrong???? |
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源代码段中缺少行号...哪一行是317行?
- 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Line numbers are missing from source snippet ... which line is line 317? - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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你没有推断任何东西。
你正在实例化。 请保持这一点,因为这不是一个微不足道的区别。 无论如何,真正的问题是你根本不应该使用这些属性。 通用映射应该有一个名为DATA_WIDTH_A的条目,您应该使用该条目而不是属性。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 You're not inferring anything. You are instantiating. Please keep this straight, as it is not a trivial distinction. Anyways, the real problem is that you should NOT use those attributes at all. The generic map should have an entry called DATA_WIDTH_A which you should use instead of the attribute. ----------------------------Yes, I do this for a living. |
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嗨,谢谢你的回复。
这是真的......它不是属性,它是通用的...... 这可以在“库指南”中轻松看到。 问候, H 以上来自于谷歌翻译 以下为原文 Hi and thank's for your reply. It's true... it's not an attribute, it's generic... This can easily be seen in the Libraries Guide . Greetings, h |
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外交官写道:
嗨,谢谢(APOSTROPHE FAIL!)的回复。 这是真的......它不是属性,它是通用的...... 这可以在“库指南”中轻松看到。 您将VHDL属性与列出的“属性”混淆,因为可以通过通用映射修改泛型来控制这些属性。 不要犯这个错误。 回到Bad Old Days,库原语不支持通用映射构造,用于控制如何构建所述原语的实例。 在某些时候,工具允许通用映射,并且有一段时间,通用映射和VHDL属性都被接受(并且在具有两者的代码中,通用映射具有优先权)。 现在,VHDL属性已被弃用,有利于使用通用映射。 删除属性,正确设置通用地图,您的设计应该继续。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 diplomat wrote: You're confusing VHDL attributes with the "attribute" listed as something that can be controlled by modifying the generic through the generic map. Do not make this mistake. Back in the Bad Old Days, the library primitives did not support the generic map construct for controlling how an instance of said primitive was built. At some point, the tools allowed generic maps, and for a while, generic maps and the VHDL attributes were both accepted (and in code that had both, the generic map had precedence). VHDL attributes are now pretty much deprecated in favor of using generic maps. Delete the attributes, set the generic map correctly, and your design should go forward. ----------------------------Yes, I do this for a living. |
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嗨贝斯曼59,
确实如此。 我读了*属性*而没有进一步思考我想到了经典的vhdl属性。 : - / 以上来自于谷歌翻译 以下为原文 Hi bassman59, that's true. I read *attribute* and without thinking further I thougt about classic vhdl attributes. :-/ |
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