VIVADO的筹码镜内存损坏

嗨，Vivado新手在这里，我已经在Vivado 2016.4 ac701设计中实例化了图标和ila核心（由ISE生成）并生成了一个位文件。
用于ila的内存似乎已损坏，我可以看到信号损坏以及附件中显示的信号。
我也在实施过程中遇到了这个消息。
[DRC 23-20]规则违规（REQP-1839）RAMB36异步控制检查 -  RAMB36E1 ........... inst_icon / U0 / U_ICON / U_CMD / G_TARGET [10] .I_NE0.U_TARGET）
有效的异步设置或复位。
当置位/复位被置位并且未被默认静态时序分析分析时，这可能导致存储器内容和/或读取值的损坏。
建议不要使用置位/复位来驱动该RAMB引脚的寄存器，或者使用同步复位，其中默认情况下复位的置位是定时的。
有没有更好的方法使用Chipcope pro工具与Vivado设计，猜猜我错过了一些重要的约束。
谢谢



以下为原文

Hi, Vivado newbie here and I've instantiated the icon and ila core(generated from ISE) in Vivado 2016.4 ac701 design and generated a bit file. The memory used for ila seems corrupted and I can see the signals corrupted as well as shown in the attachment. Also I came across this message during implementation..

[DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 .....
......inst_icon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET)
that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default
static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.


Is there a better way to use chipscope pro tool with Vivado design, guess I've missed some important constraints here.

Thanks