如何在xilinx中制作RPM？

您需要阅读约束指南的RLOC部分：
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
本应用笔记涵盖了其他一些没有详细记录的问题。
我十年前使用Virtex-II示例编写了它，但所有RPM信息仍然相关：
http://www.xilinx.com/support/documentation/application_notes/xapp416.pdf
基于切片的RPM存在一个问题，即它们需要与原点一起放置在正确的切片类型中以维持预期的相对切片位置。
如果设置了变量XIL_PAR_ALIGN_USER_RPMS并且宏围绕切片切片的最左下方切片构建，则自动放置将仅正确处理此问题。
有关宏来源的更多信息，请参阅上面的appnote。
使用FPGA编辑器检查生成的宏。
列表窗口可以设置为“用户定义的宏”，然后您可以从列表中选择它们以使它们变暗。



以下为原文

You'll want to read the RLOC section of the constraints guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
 
This appnote covers some other issues that aren't well documented. I wrote it ten years ago using a Virtex-II example, but all of the RPM information is still relevant:
http://www.xilinx.com/support/documentation/application_notes/xapp416.pdf
 
There is a problem with slice based RPMs in that they need to be placed with the origin in the correct slice type to maintain the intended relative slice positions. Automatic placement will only handle this correctly if the variable XIL_PAR_ALIGN_USER_RPMS is set and the macro is constructed around the lower left most slice of a slice tile. See the above appnote for more information about macro origins.
 
Use FPGA Editor to examine the resulting macros. The list window can be set to "User Defined Macros" and then you can select them from the list to hilight them.
 
 

嗨bwade，
我遵循指南，我设法将RLOC约束放在verilog中用于单比特FF。
例如：
（* RLOC_GRID =“GRID”*）//在模块实例化之前声明一次。
（* RLOC =“X3Y4”*）
reg sample_reg;
同样也放在其他FF上。
问题是我无法在总线上放置RLOC约束。
喜欢
reg [3：0] sample_bus;
XST只是忽略它并根据需要映射组件。
你能告诉我我可能做错了什么，或者如何在公交车上放置RLOC约束？
谢谢



以下为原文

Hi bwade,
I followed the guide and well I managed to place RLOC constraints in verilog for single bit FFs. for example:
 
 
(* RLOC_GRID =  "GRID" *) // declaring once before module instantiation.
(* RLOC = "X3Y4" *)
reg sample_reg;
 
and similarly placing on other FFs as well.
 
The problem is that I can't place RLOC constraints on buses. like
reg [3:0] sample_bus;
 
XST simply ignores it and maps the components as it likes.
 
Can you kindly tell me what i might be doing wrong or how can I place RLOC constraints on buses ?
 
Thanks
 
 

此外，当我以相同的方式将约束放置到BRAM实例时，忽略它说层次结构中没有RLOC参数。我忘了提及，我的目标设备是spartan3 xc3s4000。



以下为原文

Also, when i place the constraints in the same manner to BRAM instance, it is ignored saying that there's no parameter with RLOC in the hierarchy.
And I forgot to mention, my targeted device is spartan3 xc3s4000.

这应该是“RPM_GRID”而不是“RLOC_GRID”，但这不会对宏创建产生影响，它只会改变坐标的解释方式。
我不确定为什么你的RLOC约束没有传递给FF实例，因为这更像是一个综合问题而不是实现问题。
您始终可以使用UCF约束来更正它。
请记住，RLOC必须位于相同的层次结构块中才能创建默认集。
如果不是，则还需要应用U_SET约束。
如果宏仅包含切片逻辑，则无需使用RPM网格。
请参阅前面引用的appnote，以讨论该主题。



以下为原文

That should be "RPM_GRID" not "RLOC_GRID" but that wouldn't make a difference in the macro creation, it only changes how the coordinates are interpreted. I'm not sure why your RLOC constraints aren't getting passed to the FF instances as that's more of a synthesis issue than an implementation issue. You can always use UCF constraints to correct that. Keep in mind that the RLOCs have to be in the same hierarchy block for the default set to be created. If they're not, you need to also apply U_SET constraints. You don't need to use RPM grid if the macro only contains slice logic. See the appnote I referenced earlier for a discussion of that topic.

嗨，
我错误地写了“RLOC_GRID”，它是“RPM_GRID”，但无论如何都没关系。
好吧，我无法让它在verilog文件中工作
（* RLOC =“X3Y4”*）
reg [1：0] sample_reg;
因此，我实例化了xilinx提供的DFF宏并将其传递给了indidiual位，并且我也切换到了ucf来应用RLOC，所以是的，到目前为止我已经成功了。
但仍然无法将BRAM添加到RPM，并显示以下信息消息
映射：91  -  aes_***ox符号“***ox”具有RLOC属性，但该属性将被忽略，因为层次结构不包含具有RLOC属性的符号。
所以，现在有两个问题，
1- BRAM不接受RLOC。
2-当我在TOP模块中实例化RPM时，映射是随机的，就像我在RPM Fpga Editor窗口中看到的那样。
我不知道问题出在哪里。
我想到的另一件事是在早期版本的xilinx ISE 9.1中，我们曾经制作RPM，然后在更大的模块中实例化模块，整个过程过去发生在PAR之前，我们曾经将RPM写入UCF并生成一个新的
ngc文件，所以我们有包含RPM信息的ngc文件。
在Xilinx 13.2中，所有内容都发生在PAR中，哪个文件包含RPM信息？
谢谢。



以下为原文

Hi,
I wrote "RLOC_GRID" by mistake, it's "RPM_GRID" but it doesn't matter anyway. And well i couldn't make it work in the verilog file like
 
(* RLOC = " X3Y4" *)
reg [1:0] sample_reg;
 
 
So, I instantiated the DFF macro provided by xilinx and passed it the indidiual bits, and also I switched to ucf for application of RLOC, so yeah that way i have been successful so far. But still BRAM cannot be added to RPM and the following info msg is displayed
 
Map:91 - aes_***ox symbol "***ox" has an RLOC attribute but the attribute will be ignored because the hierarchy contains no symbols with RLOC attributes.
 
So, now two issues are at hand,
1- BRAMs are not accepting RLOC.
2- When I instantiate the RPM in the TOP module, the mapping is all random and nothing like I saw in RPM Fpga Editor's window. I don't know where the problem is.
 
Another thing I was thinking was that in older versions of xilinx ISE 9.1, we used to make RPM and then instantiate the module in larger module and that whole process used to happen before PAR, and we used to write RPM to UCF and generate a new ngc file, so we had ngc file containing RPM info.
 
Whereas in Xilinx 13.2, everything happens in PAR, which file contains the RPM info?
 
Thanks.

听起来BRAM和FF不在同一层次结构中，因此默认情况下不在相同的RPM集中。
您需要将它们与RLOC（x0y0，如果您不需要额外的偏移量）绑定在较高层级上，到它们具有公共根的位置，或者您需要使用U_SET属性显式定义该集合。
如果RPMs组件的相对位置看起来不正确，那可能是因为RPM未放置在正确的站点位置。
请参阅上面我提到的XIL_PAR_ALIGN_USER_RPMS变量，该变量可用于控制由布局器选择的站点类型。
您也可以使用RLOC_ORIGIN手动约束。



以下为原文

It sounds like the BRAM and FF are not in the same hierarchy and so not in the same RPM set by default. You either need to tie them together with RLOCs (x0y0 if you want no additional offset) on the upper hierarchy levels, to the point where they have a common root, or you need to explicitly define the set with U_SET properties.
 
If the relative placement of the RPMs components doesn't look correct, that's probably because the RPM wasn't placed in the correct site location. See above where I mention the XIL_PAR_ALIGN_USER_RPMS variable which can be used to contol the site type selected by the placer. You can also manually constrain with RLOC_ORIGIN.

嗨，
这是我的RPM的UCF。
我用U_SET和HU_SET测试了它但没有成功。
我已经附上了这个帖子的RPM模块.v文件，我无法使***ox BRAM成为与其他寄存器相同级别的一部分。
我已经做了你建议的一切，也许我做错了什么或者我错过了什么，但你能看看它，看看问题可能是什么。
INST“***ox”RLOC_ORIGIN = X0Y0; INST“***ox”RLOC = X0Y0; INST“***ox”U_SET = bytemodule; // INPUT REGSINST“KeyXorLfsr_bit0”RLOC = X2Y0; INST“KeyXorLfsr_bit0”U_SET = bytemodule; INST“KeyXorLfsr_bit1”RLOC = X3Y0
; INST“KeyXorLfsr_bit1”U_SET = bytemodule; INST“KeyXorLfsr_bit2”RLOC = X2Y2; INST“KeyXorLfsr_bit2”U_SET = bytemodule; INST“KeyXorLfsr_bit3”RLOC = X3Y2; INST“KeyXorLfsr_bit3”U_SET = bytemodule; INST“KeyXorLfsr_bit4”RLOC = X2Y4; INST
“KeyXorLfsr_bit4”U_SET = bytemodule; INST“KeyXorLfsr_bit5”RLOC = X3Y4; INST“KeyXorLfsr_bit5”U_SET = bytemodule; INST“KeyXorLfsr_bit6”RLOC = X2Y6; INST“KeyXorLfsr_bit6”U_SET = bytemodule; INST“KeyXorLfsr_bit7”RLOC = X3Y6; INST“KeyXorLfsr_bit7
“U_SET = bytemodule; // OUTPUT REGSINST”***ox_sub0“RLOC = X4Y0; INST”***ox_sub0“U_SET = bytemodule; INST”***ox_sub1“RLOC = X5Y0; INST”***ox_sub1“U_SET = bytemodule; INST”***ox_sub2“RLOC = X4Y2; INST”
***ox_sub2“U_SET = bytemodule; INST”***ox_sub3“RLOC = X5Y2; INST”***ox_sub3“U_SET = bytemodule; INST”***o
x_sub4“RLOC = X4Y4; INST”***ox_sub4“U_SET = bytemodule; INST”***ox_sub5“RLOC = X5Y4; INST”***ox_sub5“U_SET = bytemodule; INST”***ox_sub6“RLOC = X4Y6; INST”***ox_sub6“U_SET = bytemodule; INST”***ox_sub7“
RLOC = X5Y6; INST“***ox_sub7”U_SET = bytemodule;
也，
当我在顶层模块中实例化RPM时，它会中断，我的意思是映射是随机的。
我已经设置了环境变量，我试图将宏锁定到X0Y0，但没有成功。
再一次，我可能错过了一些东西。
最后一件事，在这种情况下我是否需要将RPM实例化为黑盒子，否则正常的实例化也会起作用？
到目前为止，我一直在做它作为一个黑盒子的东西，我想我通过正常的实例化尝试它，它也没有那样工作，将再次检查它。但是什么是正确的方法？
请给我一些指示。
谢谢
AES_8bit_RPM.v 7 KB



以下为原文

Hi,
Here's my UCF for the RPM. I have tested it with U_SET and HU_SET but no success.
 
I have attached the RPM module .v file with this post, I cannot make the ***ox BRAM a part of same level as other registers. I have done everything you suggested, maybe i was doing something wrong or maybe I missed something, but can you look at it and see what the problem might be.
 
INST "***ox"    RLOC_ORIGIN = X0Y0  ;
INST "***ox"    RLOC = X0Y0  ;
INST "***ox" U_SET = bytemodule;

// INPUT REGS
INST "KeyXorLfsr_bit0" RLOC = X2Y0;
INST "KeyXorLfsr_bit0" U_SET = bytemodule;

INST "KeyXorLfsr_bit1" RLOC = X3Y0;
INST "KeyXorLfsr_bit1" U_SET = bytemodule;

INST "KeyXorLfsr_bit2" RLOC = X2Y2;
INST "KeyXorLfsr_bit2" U_SET = bytemodule;

INST "KeyXorLfsr_bit3" RLOC = X3Y2;
INST "KeyXorLfsr_bit3" U_SET = bytemodule;

INST "KeyXorLfsr_bit4" RLOC = X2Y4;
INST "KeyXorLfsr_bit4" U_SET = bytemodule;

INST "KeyXorLfsr_bit5" RLOC = X3Y4;
INST "KeyXorLfsr_bit5" U_SET = bytemodule;

INST "KeyXorLfsr_bit6" RLOC = X2Y6;
INST "KeyXorLfsr_bit6" U_SET = bytemodule;

INST "KeyXorLfsr_bit7" RLOC = X3Y6;
INST "KeyXorLfsr_bit7" U_SET = bytemodule;

// OUTPUT REGS

INST "***ox_sub0" RLOC = X4Y0;
INST "***ox_sub0" U_SET = bytemodule;

INST "***ox_sub1" RLOC = X5Y0;
INST "***ox_sub1" U_SET = bytemodule;

INST "***ox_sub2" RLOC = X4Y2;
INST "***ox_sub2" U_SET = bytemodule;

INST "***ox_sub3" RLOC = X5Y2;
INST "***ox_sub3" U_SET = bytemodule;

INST "***ox_sub4" RLOC = X4Y4;
INST "***ox_sub4" U_SET = bytemodule;

INST "***ox_sub5" RLOC = X5Y4;
INST "***ox_sub5" U_SET = bytemodule;

INST "***ox_sub6" RLOC = X4Y6;
INST "***ox_sub6" U_SET = bytemodule;

INST "***ox_sub7" RLOC = X5Y6;
INST "***ox_sub7" U_SET = bytemodule;
 
 
Also,
when I instantiate the RPM in the top module, it breaks, I mean the mapping is all random. I have set the environment variable, I tried to lock the macros to X0Y0, but no success. Again, i may have missed something.
 
One last thing, do I need to instantiate the RPM as a black box in this case or normal instantiation would also work? So far, I have been doing it as a black box thing, I guess I tried it by normal instantiation, it didn't work that way too, will check it again.But what's the right way ?
 
 
 
Kindly, give me some pointers.
 
Thanks
            AES_8bit_RPM.v ‏7 KB

由于未定义的模块，此设计无法编译。
你能附上那个吗？
RROR：HDLCompilers：87  - “../../AES_8bit_RPM.v”第121行无法找到模块/原语'aes_***ox'



以下为原文

This design does not compile due to an undefined module. Can you attach that as well?
 
RROR:HDLCompilers:87 - "../../AES_8bit_RPM.v" line 121 Could not find module/primitive 'aes_***ox'

嗨，
对不起，我忘了附上BRAM模块。
我附加了包含aes_***ox BRAM的ip_core文件夹。
此外，当我在顶层模块中实例化此RPM，作为黑盒或作为普通实例时，它会中断。
我只在顶层模块中有一个RPM实例而没有别的。
模块顶部（clk，rst，key，lfsr，text_out）;输入clk;输入rst;输入[7：0]键;输入[7：0] lfsr;
output [7：0] text_out; AES_8bit_RPM inst0（.clk（clk）,. first（rst）,. KeyXorLfsr（key ^ lfsr），。sub_out（text_out））; endmodule
这是顶级模块的UCF：
NET“clk”TNM_NET =“clk”; TIMESPEC TS_clk = PERIOD“clk”8 ns HIGH 50％INPUT_JITTER 1.8 ns; NET“clk”LOC = AH15; NET“rst”PULLUP; NET“rst”LOC = AJ19; INST“
inst0“RLOC_ORIGIN = X0Y0; INST”inst0“RLOC = X0Y0; INST”inst0“HU_SET = TopSet;
HTH
ipcore_dir.rar 1547 KB



以下为原文

Hi,
Sorry I forgot to attach the BRAM module. I have attached the ip_core folder which contains the aes_***ox BRAM.
Also, when I just instantiate this RPM in a top module, as a black box or as a normal instance, it breaks. I only have one instance of RPM in top module and nothing else.
 
 
module top(
                clk
                ,rst
                ,key
                ,lfsr
                
                ,text_out

                );

input    clk;
input    rst;
input    [7:0]    key;
input    [7:0]    lfsr;
                
output [7:0]    text_out;



AES_8bit_RPM inst0(
                    
                    .clk    (clk)
                    ,.rst    (rst)
                    
                    ,.KeyXorLfsr    (key ^ lfsr)
                    
                    ,.sub_out    (text_out)
                    
                    );


endmodule
 
and here's the UCF for this top module:
 
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 8 ns HIGH 50 % INPUT_JITTER 1.8 ns;

NET "clk" LOC = AH15;

NET "rst" PULLUP;
NET "rst" LOC = AJ19;

INST "inst0" RLOC_ORIGIN = X0Y0;
INST "inst0" RLOC = X0Y0;
INST "inst0" HU_SET = TopSet;
 
 
 
HTH
            ipcore_dir.rar ‏1547 KB