是否有指示MAP的方法

我的设计具有很高的时钟频率。
我已经用流水线阶段对设计进行了编码，以解决远端块之间的互连延迟。
我使用了-shreg_extract = no来消除合成中这些触发器的移位寄存器推断。
Map仍然检测到SRL并将管道阶段转换为SRL，从而消除了互连流水线。
我可以关闭MAP中的全局优化，它不会推断SRL  - 但这有点严苛，消除了这是有益的实例。
没有迹象表明MAP已收到来自综合的任何约束，表明它不应推断某些寄存器上的SRL。
是否有指示MAP的方法，它不应该在某些信号上推断SRL？
谢谢
杰夫



以下为原文

I have a design that has high clock rates.
I have coded the design with pipeline stage to account for interconnect delays between distant blocks.
I have used -shreg_extract = no to eliminate shift register inferences of these flops in synthesis.

Map still detects SRL's and converts pipeline stages to SRL's eliminating the interconnect pipelining.

I can turn off global optimization in MAP and it will not infer SRL's - but this is a bit draconian, eliminating instances where this is beneficial.
There is no indication that MAP has received any constraints from synthesis indicating it should not infer SRL's on certain registers.

Is there a means of indicating to MAP it should not infer SRL's on some signals?

Thanks

Geoff