MAP检查设计是否适合目标设备？

嗨，
我正在阅读综合和实施过程中发生的事情，我有一个问题：
在合成期间，例如使用Synplify Pro，该设计从RTL描述转换为Xilinx原语，其以门级网表的形式描述，例如，
EDIF文件。
翻译过程将所有EDIF文件（来自综合）和/或其他NGC文件合并到NGD中（此时也添加所有UCF）。
在UG695中，它说MAP过程“为设计中的所有基本逻辑元素分配CLB和IOB资源”。
由于此处没有进行任何放置（仅在PAR期间），这里究竟发生了什么？
MAP是否仅检查设计是否适合目标设备？
（在资源和IO引脚方面）
我还希望获得用户指南的链接，详细说明每个过程中发生的情况。
谢谢
LVDS不是设计师手提包！



以下为原文

Hi,

I was reading up on what goes on during Synthesis and Implementation and I have a question:

During Synthesis for example using Synplify Pro, the design is converted from RTL description into Xilinx Primitives which is described in the form of a gate level netlist e.g. EDIF file.

The Translate Process merges all EDIF files (from synthesis) and/or additional NGC files into a NGD (all UCFs are also added at this point).

In UG695, it says that the MAP process "Allocates CLB and IOB resources for all basic logic elements in the design". Since no placement is done here (only during PAR), what exactly happens here? Does MAP only check that the design fits into the Target Device? (In terms of Resources and IO Pins)

I would also appreciate links to User Guides on detailed description of what happens during each process.

Thanks


LVDS is NOT a designer handbag!