Spartan 6 DCM LOCKED没有输出时钟

所以这很奇怪而且很间歇。
我有一个S6LX45的设计。
它使用一个PLL和八个DCM。
8个DCM时钟输入来自馈送BUFIO2的GCLK引脚。
BUFIO2分频器被禁用，DIVCLK输出进入DCM的时钟输入。
DCM仅用于相移（用于处理源同步输入数据）。
这8个DCM时钟输入来自ADC，它采用内部重新驱动的输入时钟，以便将数据时钟提供给FPGA。
FPGA中的PLL提供ADC输入时钟（它们很常见）。
八个DCM保持复位状态，直到PLL锁定为止，然后持续更长时间以确保所有ADC输出时钟（到FPGA）都在运行。
然后移除DCM重置并且所有内容都应锁定。
有一些逻辑监视每个DCM的LOCKED输出，如果它们中的任何一个消失，则DCM的复位被置位几个时钟，然后我等待大约650微秒（比指定的最大锁定时间长）并测试LOCKED
再次。
如果LOCKED仍然不为真，则重置/等待再次运行。
问题：
每隔一段时间，也许每20个电源周期，其中一个DCM拒绝工作。
它的输出时钟永远不会切换，但其DCM LOCKED标志变为真。
我已经确认输入时钟始终存在。
有什么可能导致这种情况？
----------------------------是的，我这样做是为了谋生。



以下为原文

So this is very weird and very intermittent. I have a design in an S6LX45. It uses one PLL and eight DCMs. The eight DCM clock inputs each come from a GCLK pin feeding a BUFIO2. The BUFIO2 divider is disabled, and the DIVCLK out goes to the DCM's clock input. The DCM is used only for phase shift (to deal with source synchronous input data). These eight DCM clock inputs come from an ADC, which takes an input clock which is redriven internally to provide the data clock back to the FPGA.

The PLL in the FPGA sources the ADC input clocks (they're common). The eight DCMs are held in reset until the PLL locks, and then for longer to ensure that all of the ADC output clocks (to the FPGA) are running. Then the DCM reset is removed and everything should lock.

There is logic which monitors each of the DCM's LOCKED outputs, and if any one of them goes away, that DCM's reset is asserted for several clocks, and then I wait for some 650 microseconds (longer than the specified maximum lock time) and test LOCKED again. If LOCKED is still not true, the reset/wait runs again.

The problem:

Every so often, perhaps every 20th power cycle, one of the DCMs refuses to work. Its output clock never toggles but its DCM LOCKED flag goes true. I have verified that the input clock is always present.

What could possibly cause this?
----------------------------Yes, I do this for a living.