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怎么将值分配给DCM_SP的CLKFX_DIVIDE

如何将变量值(整数)分配给DCM_SP的CLKFX_DIVIDE?
(此CLKFX_DIVIDE属于通用类型)。
变量包含时钟将被分割的值,范围为1-32。
问候。

以上来自于谷歌翻译


以下为原文

How to  assign a variable value (integer) to CLKFX_DIVIDE of DCM_SP? (where this CLKFX_DIVIDE is of generic type). The variable contains by how much value the clock will get divided, in the range of 1-32.

regards.

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曾玲娟

2019-5-14 14:13:39
你不能......
Spartan-3A Libaries Guide(spartan3a_hdl.pdf)中描述了DCP_SP接口。
CLKFX_DIVIDE是1到32之间的整数值.VLDL和Verilog都有一个示例实例化模板。
请注意,当前Spartan系列(-3,3E,-3A / AN,A DSP)上的DCM是静态配置的。
在合成设计时选择配置,并且此配置由编程配置(例如.bit文件)指定。
您无法在用户逻辑中动态更改此值。
这就是为什么这些值被描述为属性而不是块上的信号。
Virtex-4和Virtex-5上的DCM具有DRP(动态重配置端口),其中一些参数可以从用户逻辑更改。
BT
消息由timpe在01-11-2009 04:14 PM编辑

以上来自于谷歌翻译


以下为原文

You can't...
 
The DCP_SP interface is described in the Spartan-3A Libaries Guide (spartan3a_hdl.pdf).
The CLKFX_DIVIDE is an integer value between 1 and 32. There is an example instantiation template for both VHDL and Verilog.
 
Note that the DCMs on the current Spartan families (-3, 3E, -3A/AN, A DSP) are statically configured. The configuration is selected when you synthesize the design and this configuration is specified by the programming configuration (e.g. .bit file). You cannot change this value on-the fly from user logic. That is why these values are described as attributes and not signals on the block.

The DCMs on Virtex-4 and Virtex-5 have a DRP (dynamic reconfiguration port) where some of the parameters can be changed from the user logic.
 
 bt
Message Edited by timpe on  01-11-2009 04:14 PM
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