如何在S6SLX9 FPGA上从4MHz输入时钟获得80MHz时钟

请参阅此UG：http：//www.xilinx.com/support/documentation/data_sheets/ds162.pdfThanks,Yash



以下为原文

Refer this UG: http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

Thanks,
Yash

好吧，谢谢，这对我很有帮助。
因此，在DCM中使用PLL或DLL时，我有以下最小输入频率：
PLL：19MHz
DCM / DLL：5MHz
它还说：
当独立于DLL运行时，DFS支持较低的CLKIN_FREQ_DLL频率。
当只使用DFS我没有任何相位相关时，对吧？
对于我的设计，我认为这应该有效。
当我想在独立模式下使用DFS时，我是否可以通过在某种配置中使用DCM_SP来实现这一点（即没有反馈循环？）



以下为原文

Ok, thx, this helped me. So, when using PLL or the DLL in the DCM I have the following minimum input frequencies:
 
PLL: 19MHz
DCM/DLL: 5MHz
 
It also says:
When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies.
 
When only using the DFS I don't have any phase correlation, right? For my design I think this should work.
 
When I want to use the DFS in stand-alone, can I can do this by using a DCM_SP in a certain configuration (i.e. without feedback loop?)

好的，在我尝试的代码下面。
给我没有时间警告。
但显然我的硬件错误仍然存​​在，也许还有其他原因。
多谢！
--------------------------------------------------
------------------------------ Clock_Manager：DCM_SP -----------------
--------------------------------------------------
-------------通用映射（CLKDV_DIVIDE => 2.0， -  CLKDV分频值CLKFX_DIVIDE => 1， -  CLKFX输出的分频值 -  D  - （1-32）CLKFX_MULTIPLY => MULTIPLY
， -  CLKFX输出的乘法值 -  M  - （2-32）CLKIN_DIVIDE_BY_2 => FALSE， -  CLKIN除以2（TRUE / FALSE）CLKIN_PERIOD => 250.0， -  nS中指定的输入时钟周期CLKOUT_PHASE_SHIFT =>“NONE”
“， - 输出相移（NONE，FIXED，VARIABLE）CLK_FEEDBACK =>”NONE“， - 反馈源（NONE，1X，2X）DESKEW_ADJUST =>”SYSTEM_SYNCHRONOUS“， -  SYSTEM_SYNCHRNOUS或SOURCE_SYNCHRONOUS PHASE_SHIFT => 0， -
- 固定相移量（-255到255）STARTUP_WAIT => FALSE  - 延迟配置DONE直到DCM_SP LOCKED（TRUE / FALSE））端口映射（CLKIN => clk_in，CLKFX => clk_out，STATUS => dcm_status_s，RST =
> reset_dcm）;



以下为原文

Ok, below the code I tried. Gives me no timing warning. But apparently my errors on the hardware stay, maybe there is another reason for it. Thx a lot!
 
-------------------------------------------------------------------------------- Clock_Manager : DCM_SP -------------------------------------------------------------------------------- generic map (
   CLKDV_DIVIDE => 2.0, -- CLKDV divide value
   CLKFX_DIVIDE => 1,   -- Divide value on CLKFX outputs - D - (1-32)
   CLKFX_MULTIPLY => MULTIPLY, -- Multiply value on CLKFX outputs - M - (2-32)
   CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
   CLKIN_PERIOD => 250.0, -- Input clock period specified in nS
   CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
   CLK_FEEDBACK => "NONE", -- Feedback source (NONE, 1X, 2X)
   DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
   PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
   STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
   CLKIN => clk_in,
   CLKFX => clk_out,
   STATUS => dcm_status_s,
   RST => reset_dcm
);

我忘记提到“MULTIPLY”是我的实体的通用



以下为原文

I forget to mention that "MULTIPLY" is a generic of my entity

嗨，您能否详细说明您现在面临的具体问题？谢谢，Yash



以下为原文

Hi,

Could you please provide me detail what exact issue now you are facing?

Thanks,
Yash

您是否模拟了DCM实例化？
是否工作正常？我建议使用时钟向导生成实例化，并比较是否需要更新参数。
--------------------------------------------------
----------------------------别忘了回复，给予kudo并接受为解决方案---------
--------------------------------------------------
-------------------



以下为原文

Did you simulate the DCM instantiation? whether it is working fine?

I recommend to use the clocking wizard to generate the instantiation and compare if any update to the parameters is required.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------