选项31-67：设计中的LUT3单元缺少输入引脚I1上的连接

HI @奥特曼，
为了调试这个，我建议你在运行优化之前打开合成设计并找出导致错误的LUT。
通常，当LUT引脚未连接时会发生此错误。
如果需要，可以在驱动错误中提到的LUT的单元格上使用dont_touch属性。



以下为原文

HI @ottmann,
 
For debugging this, I would suggest you open the synthesized design before running optimization and find out the LUT causing the error. Generally, this error would occur when the LUT pins are unconnected.
 
If you want you can use the dont_touch attribute on the cell driving the LUT mentioned in the error.

@ottmann
这已在Vivado实施用户指南（UG904）的“常见设计错误”主题下记录：
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf#page=51
正如@ shameeraYou正确建议的那样，您可以打开精心设计或合成设计并检查LUT单元的连接。
打开合成设计后使用以下TCL命令：
show_objects -name test [get_cellsLD180_130918_i / axi_apb_bridge_0 / U0 / AXILITE_SLAVE_IF_MODULE / FSM_sequential_axi_wr_rd_cs [1] _i_2]
如果您有一个有效的连接并且该工具正在修剪它，您也可以应用DONT_TOUCH属性。
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug912-vivado-properties.pdf#page=191
FYI：HTTPS：//www.xilinx.com/support/answers/70111.html
--Syed
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以下为原文

@ottmann
 
This has been documented in Vivado implementation user guide (UG904) under "common design error" topic:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf#page=51
 
As correctly suggested by @shameera You can open elaborated or synthesized design and check the connection of the LUT cell. 
Use the following TCL command after opening synthesized design:
show_objects -name test [get_cells LD180_130918_i/axi_apb_bridge_0/U0/AXILITE_SLAVE_IF_MODULE/FSM_sequential_axi_wr_rd_cs[1]_i_2]
 
You can also apply DONT_TOUCH attribute if you have a valid connection and the tool is trimming it. 
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug912-vivado-properties.pdf#page=191
 
FYI: https://www.xilinx.com/support/answers/70111.html
 
--Syed
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