有关不需要的地图处理和无效地图选项的一些问题

我正在做一个与控制ddr sdram相关的项目，使用V2P并且必须将一个信号延迟几纳秒来捕获那些高速数据。
所以我做了一个实验，关于使用LUT来判断一个信号，看看这个技术是否可行。
然而，实施的结果不能满足我的期望。
关于映射过程和地图选项的这个问题困扰了我好几天，我真的希望有人可以给我一个建议。
以下是我的代码，d2是使用一个LUT的延迟信号：//////代码的开头////////////////////////
//////////////////////////////////////////////////
////////模块temp（输入clk，输入rst，输出reg [1：0] d1，输出d2）; wire [1：0] datain;分配datain = d1 + 1'b1; always @（
posedge clk）if（〜rst）d1 else d1 LUT4 one（.I0（1'b1），。I1（1'b1）,. I2（1'b1）,. I3（d1 [1]）,. O（
D2））;
// d2是延迟信号defparam one.INIT = 16'hff00; ///////代码的结尾
不幸的是，虽然我可以在综合后看到技术原理图中的LUT“一”，但我无法通过FPGA编辑器在Place＆amp; amp;
路线。
奇怪的是，我可以在映射过程之后使用Floorplanner看到这个LUT，我在MAP之后无法使用FPGA编辑器看到它。
然后只能通过制作这样的区域约束来阻止优化：“INST”一个“LOC =”SLICE_X7Y53“;”
以下是我对三个方面的提问：
1为什么我用来延迟信号的LUT被修剪了？
在我看来，如果电路的功能没有改变，软件可以优化实现过程。
例如，它可以在一个切片中交换两个LUT。
但在这种情况下，当没有添加约束时，输出“d2”已直接连接到寄存器“d1”的输出，这不符合我的要求。
从我上面的代码，我原来希望输出“d2”延迟一个LUT。
2如果我没有设置“-detail”选项，为什么地图报告不显示有关修剪逻辑的信息由于在实施过程中已经修剪了LUT，我真的希望这些报告向我显示相关信息。
但是，首先，我无法在地图报告的“删除的逻辑摘要”中看到有关我的LUT“one”的相关信息。
只有在我在映射过程中设置“-detail”选项后才能看到以下信息：
///地图报告中的相关部分第4节 - 删除逻辑摘要--------------------------------- 1 block
（s）优化了3个块冗余第5节 - 删除逻辑-------------------------优化块：TYPE BLOCKVCC XST_VCCRedundant Block
（s）：TYPE BLOCKLUT4 one //这是LUT4，不应该被修剪INV rst_inv1_INV_0INV Mcount_d1_xor11_INV_0 ////////报告中的冗余块是否会被修剪？
如果确实如此，无论我看到“-detail”选项，都会显示此信息。但是为什么Map进程认为这个LUT4是多余的？
是因为除了延迟信号之外这个LUT没有效果（但这是我想要的）？
我想我应该知道这些信息，并在将来注意这些逻辑，以防止不必要的逻辑删除。
否则，该工具无法实现我想要的设计。
3为什么地图选项“-u”不起作用？
第三，我尝试设置MAP命令行选项以防止修剪发生。
我使用“-u”选项意味着不删除未使用的逻辑。
但无论如何，MAP过程修剪了这个LUT。
为什么这个选项不起作用？
这个问题困扰了我好几天，周围没有人可以清楚地解释原因。
所以，如果有人能解释为什么这些工具以这种方式实现我的代码，我将深表感谢。
问候，麦克



以下为原文

I am doing a project, which is related to control ddr sdram, with V2P and have to delay one signal for several nanoseconds to capture those high-speed datas. So I have done an experiment about using LUT to dealy one signal to see whether this technique can work. However, the result of the implemention cannot meet my expectation. This problem about the mapping process and map option has puzzled me for several days and I really want someone can give me an advice.

The following is my code and d2 is the delayed signal using one LUT:
//////the start of the code
//////////////////////////////////////////////////////////////////////////////////
module temp(
input  clk,
input rst,
output reg  [1:0] d1,
output   d2
    );

wire [1:0] datain;
assign datain = d1 + 1'b1;

always @ (posedge clk)
if (~rst)
   d1 <= 0;  
else  
   d1 <= datain;
   
   
LUT4 one( .I0(1'b1), .I1(1'b1), .I2(1'b1), .I3(d1[1]), .O(d2));  //d2 is the delayed signal
defparam    one.INIT = 16'hff00;
///////the end of the code

Unfortunately, although I can see the LUT "one" in Technology Schematic after synthesis, I cannot find it through FPGA Editor after Place & Route. And the strange thing is that I can see this LUT using Floorplanner after the process of mapping and I cannot see it using FPGA Editor after MAP. And afterwards only by making an area constraint like this can I prevent the optimization: "INST "one" LOC = "SLICE_X7Y53" ;" The following are my questions of three aspects:

1 Why this LUT, which I used to delay the signal has been trimmed?

In my view, the software can optimize the process of implementation if the function of the circuit doesn't change. For example, it can swap the two LUTs in one slice. But in this case, output "d2" has been connected to the output of the register "d1" directly when no constraint has been added, which doesn't meet my requirement. From my code above, originally I want output "d2" is delayed by one LUT.


2 Why doesn't the Map report show those information about trimming the logic if I don't set "-detail" option

Since that LUT has been trimmed during the implemetation process, I really want those reports show me the relevant information. However, at first, I cannot see the relevant information about my LUT "one" in the "Removed Logic Summary" in the Map Report. Only after I set "-detail" option during mapping process can I see the following information:
///the relevant part in the map report
Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) optimized away
   3 Block(s) redundant
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE   BLOCK
VCC   XST_VCC
Redundant Block(s):
TYPE   BLOCK
LUT4   one    //this is the LUT4 which should not be trimmed
INV   rst_inv1_INV_0
INV   Mcount_d1_xor<0>11_INV_0
////////

Will the redundant block in report be trimmed? If it is true, this information should show up no matter I see "-detail" option.

But why does the Map process consider this LUT4 redundant? Is it because this LUT has no effect other than delay a signal(but this is what I wanted)? I think I should know those information and pay attention to those logics in the future to prevent unwanted logic removal. Otherwise, the tool cannot implement the design as I want.


3 Why doesn't the map option "-u" work?

Thirdly, I have tried to set the MAP command line options to prevent the trimming happen. And I have use "-u" option which means not to remove unused logic. But the MAP process trim this LUT anyway. Why doesn't this option work?


This problem has puzzled me for several days and no one around me can explain the reason clearly. So, I will deeply appreciate if someone can explain why the tools implement my code that way.  

Regards,
Mike