在我的研究工作中，Xilinx
FPGA中的大规模并行处理器阵列（例如，100s的32b RISC和6VLX240T中的路由器），我的设计使用分层RPM来平铺（并填充）设备。
这些又是由原始元素和（通常）手工技术映射的LUT构建的。
为了获得最佳的结果质量，我寻找了最小化数据路径原语的方法，例如通过使用lut_map'd LUT将多路复用器和ALU折叠成LUT，并携带合成工具仍未找到的prims。
除了手动技术映射之外，我还使用分层RLOC来管理这些模块的放置，从而获得快速且确定性的PAR运行，并从我的关键路径中削减数十个百分点。
在我的设计中，通常> 50％的基元是手工技术映射和/或手工放置。
自1995年以来，我一直使用这种方法，尽管多年来经历了一些起伏，但它一直很棒。
在准备转向Vivado for 7系列设备时，我一直在审查Vivado实施文档。
注意：我还没有使用过这些新的Vivadotools。
在UG901中，我发现在HDL中不支持lut_map和rloc属性。
在UG903中，我也没有看到对先前ISE约束指南中的RLOC约束或类似概念的支持。
是全新文档的这些mereshortcomings，还是lut_map和rloc消失了？
Xilinx是否终止了对7系列及更高版本设备的RPM的支持？
（如果RPM是历史记录：也许可以使用XCF文件中的LOC约束（其中100,000个）来克服RLOC的丢失 - 但对于不拥有顶级设计的IP供应商而言，这将无法解决。
我不知道如何解决丢失lut_map以接管关键设计元素的技术映射。）
非常感谢您对此问题的任何指导。
以上来自于谷歌翻译
以下为原文
In my research work in massively parallel processor arrays in Xilinx FPGA (e.g. 100s of 32b RISCs and routers in one 6VLX240T), my designs
tile (and fill) the device with hierarchical RPMs. These in turn are built up from primitive elements and (often) hand-technology-mapped LUTs. For very best quality of results I seek out ways to minimize datapath primitives, for example by folding muxes and ALUs into LUTs using lut_map'd LUTs and carry prims that the synthesis tools still don't find. Besides manual technology mapping, I also manage placement of these modules using hierarchical RLOCs to get fast and deterministic PAR runs and to shave many tens of per cent from my critical paths. In my designs often >50% of the primitives are hand technology mapped and/or hand placed.
I have used this methodology since 1995 and despite some ups and downs over the years, it's been great.
In preparing to move to Vivado for 7 series devices and beyond, I've been reviewing the Vivado implementation docs.
Note: I haven't used these new Vivado tools yet.
In UG901, I can find no support for lut_map and rloc attributes in HDL.
In UG903, I also don't see support for RLOC constraints or similar concepts from previous ISE Constraints guides.
Are these mere shortcomings of the brand new documentation, or are lut_map and rloc gone? Is Xilinx ending support for RPMs in 7 Series and later devices?
(If RPMs are history: Perhaps one can overcome the loss of RLOCs using LOC constraints in the XCF file (100,000s of them) -- but that won't work fwell for IP vendors who don't own the top level design. And I don't see how one can work around the loss of lut_map to take over technology mapping of critical design elements.)
Thank you very much for any guidance on this concern.
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