关于消除LATCH和gated clock，求助~

本人用VHDL作了一个ALU，但是在synthesiz和implement design时有2个警告不能消除，一个是关于latch锁存器的，我知道是ifelse语句赋值不完整造成的，但是在else逻辑里并不想改变toacc这个值，所以就消除不掉latch.
还有一个是说toacc产生了gated clock，但是我并没有把这个用作时钟信号，所以并不清楚错误产生的来源。
不知道各位大神有什么见解可以消除这两个警告吗，小弟感激不尽。
代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
    Port ( mcu2alu : in  STD_LOGIC_VECTOR(2 downto 0);
         --clk : in STD_LOGIC;
           --acc2alu : in  STD_LOGIC;
     ACC_ALU : in  STD_LOGIC_VECTOR (15 downto 0);
     MBR_ALU : in  STD_LOGIC_VECTOR (15 downto 0);
           ALU_ACC : out  STD_LOGIC_VECTOR (15 downto 0));
end ALU;
architecture Behavioral of ALU is
signal fromacc : std_logic_vector(15 downto 0):=x"0000";
signal frommbr : std_logic_vector(15 downto 0):=x"0000";
signal toacc : std_logic_vector(15 downto 0):=x"0000";
signal calready : std_logic:='1';
begin
process(calready,mcu2alu,fromacc,frommbr,toacc)
begin
if (mcu2alu/="000")then
if (calready='1')then
calready<='0';
if (mcu2alu= "001")then toacc<=fromacc+frommbr;
elsif (mcu2alu= "010")then toacc<=fromacc-frommbr;
elsif (mcu2alu= "011")then toacc<=fromacc AND frommbr;
elsif (mcu2alu= "100")then toacc<=fromacc OR frommbr;
elsif (mcu2alu= "101")then toacc<=not fromacc;
elsif (mcu2alu= "110")then toacc<=To_stdlogicvector(To_bitvector(fromacc) sll conv_integer(1));
else toacc<=To_stdlogicvector(To_bitvector(fromacc) srl conv_integer(1));
end if;
else
calready<='0';
end if;
else
calready<='1';
end if;
end process;
process(toacc)
begin
ALU_ACC<=toacc;
end process;
process(ACC_ALU,MBR_ALU)
begin
fromacc<=ACC_ALU;
frommbr<=MBR_ALU;
end process;
end Behavioral;
警告如下：
WARNING:Xst:737 - Found 16-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
PhysDesignRules:372 - Gated clock. Clock net toacc_not0000 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

0