分享FPGA的几个模块代码

实现分频器分频代码，可以将高频率波形分频到指定的低频波形：

源程序如下：

architecture Behavioral of fred is

 signal clk12M:std_logic_vector(23 downto 0):=x"000000";

 signal clk1M:std_logic_vector(23 downto 0):=x"000000";

begin

process(clk_48MHz)

begin

	if clk_48MHz'event and clk_48MHz='1' then

		if clk12M=x"B71B00" then

			clk12M<=(others=>'0');

		else 

			clk12M<=clk12M+'1';

		end if;

	end if;

end process;

clk_4Hz<='1' when clk12M=x"B71B00" else '0';

 

process(clk_48MHz)

begin

	if clk_48MHz'event and clk_48MHz='1' then

		if clk1M=x"F4240" then

			clk1M<=(others=>'0');

		else 

			clk1M<=clk1M+'1';

		end if;

	end if;

end process;

scan_48Hz<='1' when clk1M=x"F4240" else '0';

 

end Behavioral;

计数器模块代码，记录脉冲信号的脉冲个数，输出为BCD码显示。

源程序如下： 

entity m10cnt is

port(clkt,rst,en:in std_logic;

		 carry_out:out std_logic;

		  data_out:out std_logic_vector(3 downto 0)

		);

end m10cnt;

 

architecture Behavioral of m10cnt is

signal cnt:std_logic_vector(3 downto 0):="0000";

signal carryout:std_logic:='0';

begin

process(clkt,rst,en)

begin

	if rst='1' then

		cnt<="0000";

		carryout<='0';

	   else if en='1' then

		         if clkt'event and clkt='1' then 

						if cnt="1001" then 

							cnt<="0000";

							carryout<='1';

						else cnt<=cnt+'1';

							carryout<='0';

						end if;

					end if;

				end if;

	end if;

end process;

data_out<=cnt;

carry_out<=carryout; 

end Behavioral;

以下为例化语句：

ENTITY sddcounter IS

PORT(RST,EN,CLK:IN STD_LOGIC;

      Q1,Q2,Q3,Q4,Q5,Q6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

		carryout:out std_logic

		);

end sddcounter;

ARCHITECTURE BHV of sddcounter is 

SIGNAL OC2,OC3,OC4,OC5,OC6:STD_LOGIC;

component m10cnt 

PORT(   clkt,rst,en:in std_logic;

		 carry_out:out std_logic;

		  data_out:out std_logic_vector(3 downto 0)

		);

END component;

begin

u1:m10cnt PORT MAP(rst=>RST,en=>EN,clkt=>CLK,data_out=>Q1,carry_out=>OC2);

u2:m10cnt PORT MAP(rst=>RST,en=>EN,clkt=>OC2,data_out=>Q2,carry_out=>OC3);

u3:m10cnt PORT MAP(rst=>RST,en=>EN,clkt=>OC3,data_out=>Q3,carry_out=>OC4);

u4:m10cnt PORT MAP(rst=>RST,en=>EN,clkt=>OC4,data_out=>Q4,carry_out=>OC5);

u5:m10cnt PORT MAP(rst=>RST,en=>EN,clkt=>OC5,data_out=>Q5,carry_out=>OC6);

u6:m10cnt PORT MAP(rst=>RST,en=>EN,clkt=>OC6,data_out=>Q6,carry_out=>carryout);

END BHV;

锁存器代码，锁存器的作用是将计数器输出数据进行锁存，当锁存器的使能信号到来时，再把信号传送到其他电路中，这样的设计使得数据显示更加稳定，不会由于计数器输入的瞬间变化造成显示数据也产生瞬间变化。

源程序如下：

architecture Behavioral of lat is

begin

process(latcher_en,rst)

begin

if  rst='1' then

	 over_out<=over_in;

	 data_out_6<="0000";

	 data_out_5<="0000";

	 data_out_4<="0000";

	 data_out_3<="0000";

	 data_out_2<="0000";

	 data_out_1<="0000";

else

 if latcher_en'event and latcher_en='1' then

    over_out<=over_in;

	 data_out_6<=data_in_6;

	 data_out_5<=data_in_5;

	 data_out_4<=data_in_4;

	 data_out_3<=data_in_3;

	 data_out_2<=data_in_2;

	 data_out_1<=data_in_1;

 end if;

end if;

end process;

end Behavioral;