mmcm动态相移无效的原因？

输入频率为50mhz
输出频率为50mhz
输出频率相位无法调整使用（psclk，psen psinc）？
- “输出输出相位Pk-to-Pk相位” - “时钟频率（MHz）（度）周期（％）抖动（ps）误差（ps）”------------
--------------------------------------------------
------------------ CLK_OUT1 ____ 50.000 ______ 0.000 ______ 50.0 ______ 192.113 ____ 164.985 ---------------------
--------------------------------------------------
-----------“输入时钟频率（MHz）输入抖动（UI）”--------------------------
--------------------------------------------------
---- __主要______________ 50 ____________ 0.010
库ieee;使用ieee.std_logic_1164.all;使用ieee.std_logic_unsigned.all;使用ieee.std_logic_arith.all;使用ieee.numeric_std.all;
library unisim;使用unisim.vcomponents.all;
entity da_clk_dcm isport（ - 端口CLK_IN1中的时钟：std_logic; - 时钟输出端口CLK_OUT1：输出std_logic; - 动态相移端口PSCLK：在std_logic中; PSEN：在std_logic中; PSINCDEC：在std_logic中; PSDONE：输出std_logic;
- 状态和控制信号RESET：in std_logic; LOCKED：out std_logic）; end da_clk_dcm;
架构xilinx of da_clk_dcm属性为CORE_GENERATION_INFO：string;
xilinx的属性CORE_GENERATION_INFO：architecture是“da_clk_dcm，clk_wiz_v3_6，{component_name = da_clk_dcm，use_phase_alignment = true，use_min_o_jitter = false，use_max_i_jitter = false，use_dyn_phase_shift = true，use_inclk_switchover = false，use_dyn_reconfig = false，feedback_source = FDBK_AUTO，primtype_sel = MMCM_ADV，num_out_clk
= 1，clkin1_period = 20.000，clkin2_period = 10.0，use_power_down =假，use_reset =真，use_locked =真，use_inclk_stopped =假，use_status =假，use_freeze =假，use_clk_valid =假，feedback_type = SINGLE，clock_mgr_type = MANUAL，MANUAL_OVERRIDE =真
}“;
- 输入时钟缓冲/未使用的连接器信号clkin1：std_logic;
- 输出时钟缓冲/未使用的连接器信号clkfbout：std_logic;
signal clkfbout_buf：std_logic;
signal clkfboutb_unused：std_logic;
signal clkout0：std_logic;
signal clkout0b_unused：std_logic;
signal clkout1_unused：std_logic;
信号clkout1b_unused：std_logic;
signal clkout2_unused：std_logic;
信号clkout2b_unused：std_logic;
signal clkout3_unused：std_logic;
信号clkout3b_unused：std_logic;
signal clkout4_unused：std_logic;
signal clkout5_unused：std_logic;
signal clkout6_unused：std_logic;
- 动态编程未使用的信号信号do_unused：std_logic_vector（15 downto 0）;
信号drdy_unused：std_logic;
- 未使用的状态信号信号clkfbstopped_unused：std_logic;
信号clkinstopped_unused：std_logic;开始
- 输入缓冲-------------------------------------- clkin1_buf：BUFG端口映射（O =
> clkin1，I => CLK_IN1）;
- Clocking primitive -------------------------------------- - MMCM原语的实例化 -
- *未使用的输入被绑定 - *未使用的输出标记为未使用mmcm_adv_inst：MMCME2_ADV通用映射（BANDWIDTH =>“OPTIMIZED”，CLKOUT4_CASCADE => FALSE，COMPENSATION =>“BUF_IN”，STARTUP_WAIT => FALSE，DIVCLK_DIVIDE => 1，
CLKFBOUT_MULT_F => 20.000，CLKFBOUT_PHASE => 0.000，CLKFBOUT_USE_FINE_PS => TRUE，CLKOUT0_DIVIDE_F => 20.000，CLKOUT0_PHASE => 0.000，CLKOUT0_DUTY_CYCLE => 0.500，CLKOUT0_USE_FINE_PS => TRUE，CLKIN1_PERIOD => 20.000，REF_JITTER1 => 0.010）端口图 - 输出
时钟（CLKFBOUT => clkfbout，CLKFBOUTB => clkfboutb_unused，CLKOUT0 => clkout0，CLKOUT0B => clkout0b_unused，CLKOUT1 => clkout1_unused，CLKOUT1B => clkout1b_unused，CLKOUT2 => clkout2_unused，CLKOUT2B => clkout2b_unused，CLKOUT3 => clkout3_unused，CLKOUT3B =>
clkout3b_unused，CLKOUT4 => clkout4_unused，CLKOUT5 => clkout5_unused，CLKOUT6 => clkout6_unused， - 输入时钟控制CLKFBIN => clkfbout_buf，CLK
IN1 => clkin1，CLKIN2 =>'0'， - 总是选择主输入时钟CLKINSEL =>'1'， - 动态重配置端口DADDR =>（其他=>'0'），DCLK =>
'0'，DEN =>'0'，DI =>（其他=>'0'），DO => do_unused，DRDY => drdy_unused，DWE =>'0'， - 用于动态相移的端口PSCLK =>
PSCLK，PSEN => PSEN，PSINCDEC => PSINCDEC，PSDONE => PSDONE， - 其他控制和状态信号LOCKED => LOCKED，CLKINSTOPPED => clkinstopped_unused，CLKFBSTOPPED => clkfbstopped_unused，PWRDWN =>'0'，RST => RESET
）;
- 输出缓冲------------------------------------- clkf_buf：BUFG端口映射（O =>
clkfbout_buf，I => clkfbout）;
clkout1_buf：BUFG端口映射（O => CLK_OUT1，I => clkout0）;
结束xilinx;