如何阅读理解Spartan6数据表？

当然，你永远不会在现实世界中达到如此完美的常数和平等，但我会假设你只是在理论上说话。
1.总是很好看看FPGA编辑器，让自己说服IOB中的触发器正在被使用。
使用时钟缓冲器和时钟树分配时钟，然后任何两个引脚之间的偏差应该不比数据表数字差。
2.正确，您将在触发器和引脚之间进行布线，它们在路径长度上的差异很可能会增加引脚之间的偏移。
关键点在于，当您使用全局时钟缓冲器，时钟树和I / O触发器等专用资源时，您可以消除布局和布线过程中的任何变化（对于工具的信号路由，没有任何选择）
解决）。
Ken Chapman英国Xilinx主要工程师
在原帖中查看解决方案



以下为原文

Of course you would never achieve such perfect constants and equality in the real world but I'll assume you are only talking in theoretical terms.
 
1. Always good to have a look in FPGAeditor to convince yourself that the flip-flops inside the IOBs are being used. Providing the clock was distributed using a clock buffer and clock tree then the skew between any two pins should be no worse than the data sheet figure.
 
2. Correct, you would then have routing between the flip-flops and the pins and their differences in path lengths would most likely increase the skew between pins. 
 
The key point is that when you use the dedicated resources such as global clock buffers, clock trees and I/O flip-flops you take away any variability in the place and route process (i.e. there are no options for the routing of signals for the tools to solve). 
Ken Chapman
Principal Engineer, Xilinx UKView solution in original post

顺序元素是时钟控制的任何元素（通常由时钟信号的上升沿）。
所以，是的，它与I / O块中的触发器有关。
它还涉及逻辑片，DSP48块和BRAM等中的触发器。如果你没有在给定块中使用触发器（例如I / O块），那么显然时钟偏差参数变得无关紧要。
由于设备中时钟树的精心设计，时钟偏差很小。比从时钟中扩展出来的时钟导致接近时钟的接近时钟元件接收时钟的时钟树，时钟树意味着所有元素都接收到
时钟边缘几乎在同一时间。如果元件位于物理上靠近时钟源，那么时钟实际上将被路由到中心点的时钟树上，然后再次路由回来。
这样可以更好地平衡所有元素的延迟。但是，当两个同步元件（例如I / O中的触发器）在物理上彼此靠近时，它们之间的时钟偏差将非常小，因为它们都将连接到
时钟树的同一'分支'的'twig'相同。
TIOPI和TIOPO是最大值（数据手册中的大多数规格）。
所以是的，它们对于每个I / O都是相同的，在实践中你会期望看到更快的东西。
也就是说，不要忘记当你看一个输出信号时，需要一段时间才能达到你认为它已经改变状态的阈值电压。所以负载和电容都有效。
Ken Chapman英国Xilinx主要工程师



以下为原文

Sequential elements are any elements that are clocked (typically by the rising edge of a clock signal). So yes, it relates to the flip-flops in I/O blocks. It also relates to flip-flops in logic Slices, DSP48 blocks and BRAMs etc. If you don't use the flip-flops in a given block (e.g. an I/O block) then clearly the clock skew parameter becomes irrelevant.
 
The clock skew is small because of the careful design of the clock trees in the device. Rather than the clock just spreading out from a source resulting in near elements receiving the clock first and far elements receiving the clock much later, the clock tree means that all elements receive the clock edge at almost the same time. In the case of the element that is located physically close the clock source, then the clock actually would have been routed onto the clock tree at a central point and then routed back again. This results in far better balance of delays to all elements. However, when two synchronous elements (e.g. flip-flops in I/O) are physically close to each other the clock skew between them will be incredibly small because they will both be connected to the same 'twig' of the same 'branch' of the clock tree.  
 
TIOPI and TIOPO are maximum values (as are most specifications in the data sheet). So yes, they are the same for every I/O and in practice you would expect to see something somewhat faster. That said, don't forget that when you look at an output signal it takes time to rise to reach the threshold voltage at which you consider it to have changed state. So loading and capacitance have an effect etc.  
 
Ken Chapman
Principal Engineer, Xilinx UK

嗨！
谢谢你的答案！
只是为了仔细检查：
让我们拥有恒定的电源，恒定的温度，相同的引脚负载，相同的转换，引脚电流速率和vout电平。
reg out; reg [7：0] DataOut;总是@（posedge clk_from_pll）开始Out DataOut结束
1.当我为这些元素设置属性IOB = TRUE时，在FPGA引脚上设置一个LOC，这意味着所有这些元素都放在IOB中，它们都是I / O顺序。
是正确的？
所以现在我可以确定在更换任何这些信号之间的最大延迟（片上球/引脚）是时钟偏差形式数据表+数据表中的封装偏差。
是正确的？
在恒温和电源供应时TIOPO对于所有引脚都是相同的，或者对于不同的引脚可能有不同的参数值，只是数据表值不多？
2.如果我设置IOB = FALSE，现在这个元素没有放在IOB中，而且它不是I / O顺序，因此我没有数据表时钟偏差值，是否正确？
或者所有的时钟元素都是I / O顺序？
为什么我在ISE报告表中看到所有项目的时钟偏差值约为0.79 ns，在数据表中最大时钟偏差为0.22？
所以...当我想控制数据总线偏斜时，我应该在IOB中设置数据总线，并尽可能减少偏斜。
如果out不在IOB中，我没有数据表的偏差值。
是正确的？



以下为原文

Hi!
 
thankyou for answer!
 
Just for double check:
 
Let we have constant power supply, constant temperature, equal load of pins, the same slew, pin current rate and vout levels.
 
reg Out;
reg [7:0] DataOut;
always @(posedge clk_from_pll)
begin
  Out <= ....;
  DataOut <= ....;
end
 
1. When I set attribute IOB = TRUE for this elements, an LOC it on FPGA pins, this mean what all of this element placing in IOB and they all is I/O sequential. Is correct?

So now I can be shure what max delay between changing of any of this signals (right on chip ball/pin) is Clock Skew form datasheet + Package Skew from datasheet. Is correct?
In constant temperature and power supply TIOPO is the same for all pin, or possible different value of this parameter for different pins, just not more what datasheet value?

2. If I set IOB = FALSE, now this element is not placed in IOB and it is not I/O sequential, and for this reason I Haven't datasheet clock skew value, is correct?
Or all of clocked element is I/O sequential? Why I see in ISE report table with clock skew value about 0.79 ns for all project, when in datasheet max clock skew 0.22?
So... When I want to controll data bus skew i should set data bus out in IOB, and have minimum possible skew. If out is not in IOB I haven't datasheet value of skew. Is correct?

当然，你永远不会在现实世界中达到如此完美的常数和平等，但我会假设你只是在理论上说话。
1.总是很好看看FPGA编辑器，让自己说服IOB中的触发器正在被使用。
使用时钟缓冲器和时钟树分配时钟，然后任何两个引脚之间的偏差应该不比数据表数字差。
2.正确，您将在触发器和引脚之间进行布线，它们在路径长度上的差异很可能会增加引脚之间的偏移。
关键点在于，当您使用全局时钟缓冲器，时钟树和I / O触发器等专用资源时，您可以消除布局和布线过程中的任何变化（对于工具的信号路由，没有任何选择）
解决）。
Ken Chapman英国Xilinx主要工程师



以下为原文

Of course you would never achieve such perfect constants and equality in the real world but I'll assume you are only talking in theoretical terms.
 
1. Always good to have a look in FPGAeditor to convince yourself that the flip-flops inside the IOBs are being used. Providing the clock was distributed using a clock buffer and clock tree then the skew between any two pins should be no worse than the data sheet figure.
 
2. Correct, you would then have routing between the flip-flops and the pins and their differences in path lengths would most likely increase the skew between pins. 
 
The key point is that when you use the dedicated resources such as global clock buffers, clock trees and I/O flip-flops you take away any variability in the place and route process (i.e. there are no options for the routing of signals for the tools to solve). 
Ken Chapman
Principal Engineer, Xilinx UK