更新Spartan6 CRC校验和失败

在我进行数据包修改后，我尝试更新Spartan6 CRC校验和失败。
这不是Virtex / E / 2 / 2P / 4/5/6/7或Spartan3E的问题，但Spartan6完全不同。
我知道Spartan6数据包由16位字组成，与上面列出的其他体系结构的32位字不同。
UG380还声明“循环冗余校验寄存器使用标准的32位CRC校验和算法。”
我可能不正确的假设是多项式与Virtex4 / 5/6/7族相同的CRC-32C（Castagnoli）多项式。
我还假设只有“有效载荷字”（在数据包标题之后）计入计算，UG380明确地将地址长度显示为6位。
如果有人关心我正在尝试使用的逻辑，那么它与所有其他Xilinx架构师的工作原理非常相似：
//开始CRC计算
uint32_t address = 0;
iterator p = begin（）;
iterator e = end（）;
//用于Virtex4 / 5/6/7系列的CRC-32C（Castagnoli）多项式
boost :: crc_basic crc32（0x1edc6f41,0,0，false，true）;
而（P
//查找当前数据包
const Spartan6Packet＆amp;
packet = * p ++;
//仅处理具有非零有效负载长度的写入数据包
if（！packet.isWrite（））继续;
address = packet.getAddress（）;
uint32_t wordCount = packet.getWordCount（）;
if（wordCount == 0）继续;
// CRC寄存器写（这是比较预期和提供的CRC值）
if（address == crcRegister）{
printf（“预计CRC32：％8.8x  n”，（uint32_t（packet [1]）
printf（“Calculated CRC32：％8.8x  n”，crc32.checksum（））;
*（p-1）= Spartan6Packet :: makeType1Write（crcRegister，crc32.checksum（））;
crc32.reset（）;
// reset CRC命令
} else if（address == cmdRegister＆amp;＆amp; wordCount> = 1＆amp;＆amp; packet [1] == rcrcCommand）{
crc32.reset（）;
//处理数据包内容
} else {
uint32_t j;
uint32_t掩码;
for（uint32_t i = 1; i
uint32_t word = packet ;
// printf（“地址：％4.4x  n”，地址）;
// printf（“Word：％8.8x  n”，字）;
for（j = 0，mask = 1; j
crc32.process_bit（（word＆amp; mask）？1：0）;
}
for（j = 0，mask = 1; j
crc32.process_bit（（地址和掩码）？1：0）;
}
}
//处理Virtex2和Virtex2P上的自动CRC
if（autoCrc＆amp;＆amp; address == fdriRegister）{
printf（“预期的自动CRC32：％8.8x  n”，（uint32_t（（* p）[0]）
printf（“Calculated Auto CRC32：％8.8x  n”，crc32.checksum（））;
* p = Spartan6Packet（crc32.checksum（））;
//当前数据包是FDRI，接下来是自动CRC
crc32.reset（）;
}
}
}
有什么建议么？

以上来自于谷歌翻译

以下为原文

I am unsuccessfully trying to update Spartan6 CRC checksums after I make packet modifications.  This is not a problem for Virtex/E/2/2P/4/5/6/7 or for Spartan3E, but Spartan6 is a different story altogether.

I know that Spartan6 packets consist of 16-bit words, unlike the 32-bit words of the other architectures listed above.  UG380 also states that "The Cyclic Redundancy Check register utilizes a standard 32-bit CRC checksum algorithm."  My perhaps incorrect assumption is that the polynomial is the same CRC-32C (Castagnoli) polynomial as for Virtex4/5/6/7 families.  I am also assuming that only "payload words" (after the packet header) factor into the calculation, and UG380 explicitly shows the address length as 6 bits.

If anyone cares to see the logic I'm trying to use, it's quite similar to what works correctly all the other Xilinx architecturs:

// begin CRC calculation
uint32_t address = 0;
iterator p = begin();
iterator e = end();
// CRC-32C (Castagnoli) polynomial for Virtex4/5/6/7 families
boost::crc_basic<32> crc32(0x1edc6f41, 0, 0, false, true);
while(p < e) {
    // look up the current packet
    const Spartan6Packet& packet = *p++;
    // only process write packets with non-zero payload length
    if(!packet.isWrite()) continue;
    address = packet.getAddress();
    uint32_t wordCount = packet.getWordCount();
    if(wordCount == 0) continue;
    // CRC register write (this is what compares the expected and supplied CRC values)
    if(address == crcRegister) {
        printf("Expected CRC32:   %8.8xn", (uint32_t(packet[1]) << 16) | packet[2]);
        printf("Calculated CRC32: %8.8xn", crc32.checksum());
        *(p-1) = Spartan6Packet::makeType1Write(crcRegister, crc32.checksum());
        crc32.reset();
    // reset CRC command
    } else if(address == cmdRegister && wordCount >= 1 && packet[1] == rcrcCommand) {
        crc32.reset();
    // process packet contents
    } else {
        uint32_t j;
        uint32_t mask;
        for(uint32_t i = 1; i <= wordCount; i++) {
            uint32_t word = packet;
            //printf("Address: %4.4xn", address);
            //printf("Word: %8.8xn", word);
            for(j = 0, mask = 1; j < 16; j++, mask <<= 1) {
                crc32.process_bit((word & mask) ? 1 : 0);
            }
            for(j = 0, mask = 1; j < addressLength; j++, mask <<= 1) {
                crc32.process_bit((address & mask) ? 1 : 0);
            }
        }
        // process the Auto CRC on Virtex2 and Virtex2P
        if(autoCrc && address == fdriRegister) {
            printf("Expected Auto CRC32:   %8.8xn", (uint32_t((*p)[0]) << 16) | (*p)[1]);
            printf("Calculated Auto CRC32: %8.8xn", crc32.checksum());
            *p = Spartan6Packet(crc32.checksum()); // current packet is FDRI, next is Auto CRC
            crc32.reset();
        }
    }
}
Any suggestions?