PSoC5LP的设计计时失败

当有一个错误在一个组件，你应该创建一个例如我或它作为一种新的线程在PSoC软件结合一些实例等。
修改一个组件会导致创建你自己的。使用一个不同的名字是我必须要做的：把事情出错，´没有人能看到你用了一个不同的（改性）成分。
鲍勃



     以下为原文
  When there is an error within a component you should create a MyCase or post it as a new thread under PSoC Software together with a bit of example etc.
    Modifying a component will always result in creating your own one. Using a different name is IMHO a must-do: Take the case that something goes wrong and ´nobody is able to see that you used a different (modified) component.
     
    Bob

我想你正在寻找一种修改SAR组件的方法。这里有一个视频说明如何将组件导入到项目中。然后，您可以根据需要修改实现。
HTTP://Vio.CyPress .COM/VIET/LabVIEO/VIDEO/COMPATIO/PSOC创建者-教程-导入组件/20676818181
！！！！危险！！！！
我不知道SAR是否可以安全地与除西斯克以外的任何东西同步。您可能会解决静态时序问题，但会产生新的问题。如果你仍然有STA问题，我怀疑它实际上不是SAR。我建议和我们的技术支持人员一起解决这个问题。我们的组件是精心设计和实施的-这个时钟很可能被“埋没”，没有选择改变频率，原因很好。
--马克。



     以下为原文
  I think you are looking for a way to modify the SAR component. Here is a video explaining how to import a component into your project. You can then modify the implementation as needed.
    http://video.cypress.com/video-library/video/Corporate/PSoC-Creator-Tutorial-Importing-Components/2067468818001
    !!! DANGER !!!
    I have no idea whether the SAR can be safely clocked with anything other than SYSCLK. You might resolve your static timing issue but create a new problem. if you are still having an STA problem I suspect it is NOT actually the SAR at all. I recommend working with our tech support people to resolve this issue. Our components are carefully designed and implemented - this clock is probably "buried", with no option to change the frequency, for  good reason.
    -- Mark.

联系技术支持文件一案
在柏树创建一个技术案例
CyPress网站
“支持”
“技术支持”
“创造一个案例”
问候，Dana。



     以下为原文
  To contact tech support file a CASE -

   

         
                  
    To create a technical case at Cypress -
     
    www.cypress.com
    “Support”
    “Technical Support”
    “Create a Case”
     
    Regards, Dana.

哇，两个非常翔实的答案！非常感谢您抽出时间来应对，这是真正的赞赏。
史葛，你所描述的组件是什么，宏是帮助很大。看来，就像你说的，在图书馆的大部分组件实际上是宏。在我看来，虽然序列SAR组件是一个实际的组件（蓝色钻石图标）。我可以，但是，“打破”它，看到它的组成的adc_sar块（黄头）和一个Verilog成分黄色块。也有其他位（虚拟的MUXes和一个中断线）在那里，但组件实际上是由几个较小的块。我的问题是，什么是“官方”或“批准”或“推荐”的方式采取的成分如序列SAR组件和修改。在我的情况下，这意味着增加两同步器的EOS和sar_adc块和各自的输入输出之间的Verilog模块EOC。
我想阅读组件作者的记录现在，我怀疑它会回答一些“新手”的问题，我有。谢谢你的指教。
不幸的是，链接是非常有帮助的；序列SAR组件是在现有的图书馆，而不是另一个项目或一个存档。我可以看到“在”在图书馆的一个组成部分是打开图浏览目录树文件系统上的唯一途径，选择页面上的所有内容和复制那些“内部”分到我的设计，我可以休息，他们需要的连接线。
我看到你和另一个时钟驱动的SAR的潜能问题预警和欣赏它；它是一个有效的关注，我会用我自己的试验和柏树。如上所述，在www.cypress .com /，我能够通过插入ADC组成数字输出和Verilog数字分量输入之间的同步满足时间。这让我在一个简单的设计或48MHz的与更复杂的去64mhz。我需要测试系统在48MHz的版本以确保操作正确但在审查的verilog代码，我不明白为什么它不工作。



     以下为原文
  Wow, two excellent and informative answers! Thank you very much for taking the time to respond, it's truly appreciated.
     
    Scott, your description of what a component is and what a macro is helps considerably. It seems, like you said, that most of the components in the library are actually macros. In my particular case, though, the Sequencing SAR component is an actual component (blue diamond icon). I can, however, "break in" to it and see that it's made up of the ADC_SAR block (yellow header) and a yellow block which is the Verilog component. There are also other bits (virtual MUXes and an interrupt line) in there, but the component is actually made up of several smaller blocks. My question was what is the "official" or "sanctioned" or "recommended" way to take a component such as the Sequencing SAR component and modify it. In my case it means adding two synchronizers between the eos and eoc outputs of the SAR_ADC block and their respective inputs in the Verilog block.
     
    I intend on reading the component author documentation now, as I suspect that it will answer some of the more "newbie" questions I have. Thanks for the pointer.
     
    Unfortunately that link was not very helpful; the Sequencing SAR component is in the existing library, not another project or an archive. The only way I can see to "get in" to a component in the library is to open up the schematic by navigating through the directory tree on the filesystem, select everything on the page and copying those "internal" compnents into my design where I can then break the connections and wire them as needed.
     
    I see your warning about the potenital issues with driving the SAR with an alternate clock and appreciate it; it's a valid concern and I will follow up with my own testing and with Cypress. As mentioned above and also over at www.cypress.com/, I was able to meet timing by inserting a synchronizer between the ADC component digital outputs and the Verilog component digital inputs. This allowed me to get to 64MHz on a simpler design and 48MHz with a more complex one. I need to test the system yet in the 48MHz version to make sure operation is correct but after reviewing the Verilog code I don't see why it would not work.

看起来像用户KEES已经写了一篇很好的文章，涵盖了（然后是一些）我正在寻找的：HTTPS://SeCur.CyPress。APP =论坛和ID ID＝2492和；RID＝78387



     以下为原文
  It looks like user kees has writting up a pretty good article that covers (and then some) what I was looking for: https://secure.cypress.com/?app=forum&id=2492&rID=78387