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我正在尝试使用串行从属配置写入Spartan-6 XC6SLX4。
我遇到了最常见的错误,即DONE没有达到高位。 我搜索了一些可能的解决方案并检查了一些非常类似的问题,但没有解决我的情况.FPGA处于3V3电压(包括VCCAUX),引脚VCCINT为1V2。 配置引脚通过4K7电阻连接到3V3 .DONE引脚具有330R上拉电压,用于3V3,而CCLK,INITB和PROGB引脚具有4k7上拉电压,用于3V3。 DIN引脚直接连接。我们用于记录的二进制文件具有以下开头并且正在发送形式(在0xFF首字母之后):1010 1010 1001 1001 0101 0101 1001 1001(MSB优先).FF FF FF FFFF FF FF FFFF FF FF FFFF FF FF FFAA 99 55 6630 A1 00 0720 00 31 A1 即使在数据流量结束后,我仍然发送时钟信号,希望DONE信号应答,但没有任何反应。 信号的一些图像,其中: 黄色 - PROG_B 绿色 - INIT_B 粉红色 - CCLK 紫色 - DIN。 对我能做什么的任何建议? 以上来自于谷歌翻译 以下为原文 I'm trying to write to a Spartan-6 XC6SLX4 using the serial slave configuration. I'm having the most common error that is the DONE does not go to high. I googled some possible solutions and checked some very similar problems, but none solved my situation. The FPGA is on 3V3 voltage (including VCCAUX) and pins VCCINT are 1V2. Configuration pins are connected to 3V3 with a 4K7 resistor. The DONE pin is with a 330R pull-up for 3V3, whereas the CCLK, INITB and PROGB pins are with a 4k7 pull-up for 3V3. The DIN pin is connected directly. Our binary file used for recording has the following beginning and sending is being in the form (after the 0xFF initials): 1010 1010 1001 1001 0101 0101 1001 1001 (MSB first). FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF AA 99 55 66 30 A1 00 07 20 00 31 A1 Even after the end of the data traffic I still sending clock signal hoping that the DONE signal answer, but nothing happens. Some images of the signal, where: Yellow - PROG_B Green - INIT_B Pink - CCLK Purple - DIN. Any suggestions of what I can do? |
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9个回答
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连接到DONE引脚的任何其他东西可能会阻止它变高?
INIT_B不会回低,这是一个好兆头。 您的启动时钟是否可能未在bitgen设置中设置为默认CCLK? 您可以连接JTAG电缆并从Impact的调试菜单中读取配置状态吗? 也许这会让人更深入了解情况。 - Gabor 以上来自于谷歌翻译 以下为原文 Anything else connected to the DONE pin that might prevent it from going high? INIT_B is not going back low, which is a good sign. Is it possible that your startup clock is not set to the default CCLK in the bitgen settings? Can you hook up a JTAG cable and read the configuration status from the debug menu of Impact? Perhaps that will give more insight into the situation. -- Gabor |
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对我来说,所有给定的范围信号似乎都可以。
请检查模式引脚。 还要检查“完成”引脚PCB走线是否短路 可能是状态寄存器位提供了一些线索,如在其他回复中提到的那样。 _______________________________________________如果有助于解决您的查询,请将此帖子标记为“接受为解决方案”。 因此,它将有助于其他论坛用户直接参考答案。如果您认为该信息有用且面向答复,请给予此帖子称赞。 以上来自于谷歌翻译 以下为原文 For me all given scope signals are seems to be OK. Please check mode pins. Also check whether any short at 'Done' pin PCB track May be status register bits gives some clues as it mentioned in other reply. ________________________________________________ Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer. Give kudos to this post in case if you think the information is useful and reply oriented. |
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Rfernandoafr
你怎么能监控编程过程? 你使用调试工具还是那样的? 我不知道我是如何实际监控这些过程的... 你可以帮帮我吗? 以上来自于谷歌翻译 以下为原文 Rfernandoafr How could you monitor programming process? Do you use debugger tool or something like that? I don't know how i can monitor these processes virtually... could you help me? |
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嗨伙计们,谢谢你们的消遣。
Gabor和Kodali:1。 DONE引脚只有330R上拉电阻连接到它。 我尝试的不仅仅是一个电路板,所以我认为这不是装配中的问题,我检查了项目中DONE引脚的轨道并且没有连接任何东西。 对不起,我是整个FPGA写入过程的新手。 我没有找到这个设置,你能告诉我更多关于它的细节吗?3。 我尝试了,但是无法使用JTAG读取FPGA配置状态。生成:你是什么意思?我正在使用IAR IDE来编程和调试正在进行FPGA写入过程的处理器。 并使用Osciloscope测量信号。 并且整个过程已在定制板中进行了调试。 以上来自于谷歌翻译 以下为原文 Hi guys, thanks for the sugestions. Gabor and Kodali: 1. The DONE pin only have the 330R pull-up resistor conected to it. I tried in more than a board, so I think that is not a problem in the assembly and I checked the track of the DONE pin in the project and does not have anything connected. 2. Sorry, I am newbie in this entire FPGA write process. I didnt find this settings, can you tell me more details about it? 3. I tried, but cant read the FPGAs configuration status using the JTAG. Generation: What do you mean? I am using the IAR IDE to program and debug the processor that is doing the FPGA write process. And using an Osciloscope to mensure the signals. And the entire process had been debugged in a custom board. |
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对不起,我忘记了模式引脚。
它们仅通过4k7电阻连接到3V3。 以上来自于谷歌翻译 以下为原文 Sorry, I forget abou the mode pins. They are only connected to 3V3 with a 4k7 resistor. |
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对不起,我是整个FPGA写入过程的新手。
我没有找到这个设置,你能告诉我更多关于它的细节吗? 我想你在谈论启动时钟设置? Bitgen默认使用CCLK作为启动时钟,但您可以将其更改为JTAG(TCK),或者“USER”wchih需要在不同引脚上设置时钟以启动设备。 请注意,在配置结束时,FPGA会经历一个可在bitgen设置中编程的启动序列。 如果使用ISE Navigator GUI,则启动设置有自己的选项卡。 如果您运行命令行工具,您应该查找bitgen的设置。 我在GUI上附加了一个屏幕截图,显示了适用于您的情况的默认启动设置。 - Gabor 以上来自于谷歌翻译 以下为原文 2. Sorry, I am newbie in this entire FPGA write process. I didnt find this settings, can you tell me more details about it? I guess you're talking about the startup clock setting? Bitgen defaults to using CCLK as the startup clock, but you can change this to JTAG (TCK), or "USER" wchih would need a clock on different pins for the device to start up. Note that at the end of configuration, the FPGA goes through a startup sequence that is programmable in the bitgen settings. Startup settings have their own tab if you use the ISE Navigator GUI. If you run command-line tools you should look up the settings for bitgen. I'm attaching a screen shot from the GUI showing the default startup settings which should work for your case. -- Gabor |
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嗨Gabor,谢谢你的回答。
启动时钟默认设置为CCLK。 以上来自于谷歌翻译 以下为原文 Hi Gabor, thanks for answer. The Start-up clock is setted for default, CCLK. |
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您是否可以发布原理图的一部分,显示与配置相关的连接?
我唯一能想到的是可能存在一些不正确的连接。 请注意,如果您的CCLK和/或DIN信号指向错误的引脚,或者您选择的模式不正确,则INIT_B输出将相同(尽管根据您对上拉的描述,1 1是正确的)。 您是否通过ug380查看图中是否有任何未实现的内容? - Gabor 以上来自于谷歌翻译 以下为原文 Can you post a section of your schematic showing the configuration-related connections? The only thing I can think is that there may be some incorrect connection. Note that the INIT_B output would lok the same if your CCLK and / or DIN signal went to the wrong pin, or you selected the incorrect mode (although 1 1 is correct according to your description of pullups). Have you looked through ug380 to see if there's anything in the diagrams there that you didn't implement? -- Gabor |
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