请问BSCAN是什么？

它是JTAG链的内部连接。
您可以在Spartan-3E文档的配置部分找到更多信息。
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如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

It is internal connections to the JTAG chain.  You can find out more about in the configuration section of the Spartan-3E documentation.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

mcgett写道：它是JTAG链的内部连接。
您可以在Spartan-3E文档的配置部分找到更多信息。
是的，我已经读过了
但是有一段时间从mbmber那里赦免它会更好
我们可以将jtag连接到MY INPUT fpga设计???
pelase帮助做到这一点
我从ken那里读到了jtag loader，但是使用块内存是一个方法吗？
最好的祝福
--------------------------------------------------
-------------------------------------------我厌倦了传统
人民 - 我想要的是与我爱的女孩一起自由生活 - 但这是不可能的，因为人民的传统比我强.------------------
--------------------------------------------------
--------------------------



以下为原文

mcgett wrote:
It is internal connections to the JTAG chain. You can find out more about in the configuration section of the Spartan-3E documentation.

yes i have read it
but some time when expalin it from mbmber it better
can we connect  jtag to MY INPUT  fpga design  ???
pelase help in doing that
i read about jtag loader from ken but is thier a methos with using block memory??


BEST REGARDS
---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples                                                       --
All I want is to live freely with the girl which I love                                   --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------

BSCAN块允许将JTAG接口扩展到内部USER定义的扫描链。
ChipScope和PicoBlaze加载程序使用此功能，这就是您在使用这些功能时看到BSCAN块出现在设备利用率报告中的原因。
可以使用内部USER扫描链和自定义逻辑来读取或写入Block RAM，然后您需要开发在PC上运行的自定义软件代码来执行此操作。
PS：看来你不是母语为英语的人，这使你的帖子难以阅读和理解。
发布前请使用“拼写检查”选项。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

The BSCAN block enables an extension of the JTAG interface to internal USER defined scan chains.  This capability is used by ChipScope and by the PicoBlaze loader which is why you see the BSCAN block appear in the device utilization reports when you use these functions.
 
It is possible to use the internal USER scan chain and custom logic to read or write to a Block RAM you would then need develop custom software code running on your PC to do this.   
 
PS:  It appears that you are not a native english speaker and this makes your posts hard to read and understand.  Please use the "Spell Check" option before posting. 
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

mcgett写道：
BSCAN块允许将JTAG接口扩展到内部USER定义的扫描链。
ChipScope和PicoBlaze加载程序使用此功能，这就是您在使用这些功能时看到BSCAN块出现在设备利用率报告中的原因。
可以使用内部USER扫描链和自定义逻辑来读取或写入Block RAM，然后您需要开发在PC上运行的自定义软件代码来执行此操作。
PS：看来你不是母语为英语的人，这使你的帖子很难阅读和理解。
发布前请使用“拼写检查”选项。
亲
谢谢你的解释
是的我不是母语英语，我每次都使用拼写检查，但在最后一次按摩时我忘了这样做。抱歉
在上一条消息中有一个印刷错误，右边是我想知道我是否可以直接使用块ram连接Bscan到我的系统？如果这样的方法是OKAnd existssis他们和VHDL模板？
最好的regrds
--------------------------------------------------
-------------------------------------------我厌倦了传统
人民 - 我想要的是与我爱的女孩一起自由生活 - 但这是不可能的，因为人民的传统比我强.------------------
--------------------------------------------------
--------------------------



以下为原文

mcgett wrote:
The BSCAN block enables an extension of the JTAG interface to internal USER defined scan chains.  This capability is used by ChipScope and by the PicoBlaze loader which is why you see the BSCAN block appear in the device utilization reports when you use these functions.
 
It is possible to use the internal USER scan chain and custom logic to read or write to a Block RAM you would then need develop custom software code running on your PC to do this.   
 
PS:  It appears that you are not a native English speaker and this makes your posts hard to read and understand.  Please use the "Spell Check" option before posting. 

dear 
thank you for explain
yes I am not native English and I am every time use spell check but in last massage I forget to do that .Sorry 
There is a typographic error In the previous message and the right is
I wondering if I can  connect Bscan to my system directly with out use block ram ??
if such method is OK And exists
is their and VHDL template??
best regrds
 
 
---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples                                                       --
All I want is to live freely with the girl which I love                                   --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------

有关边界扫描的一般信息，请参阅XAPP070应用说明。
边界扫描（JTAG）配置模式使您可以在任何JTAG兼容设备链上执行基于边界扫描的配置操作。
该链可以包含Xilinx®和非Xilinx器件，但只有BYPASS和HIGHZ操作可用于非Xilinx器件。
边界扫描是最流行的配置模式，因为它具有标准化能力，能够通过相同的四个JTAG引脚对FPGA，CPLD和PROM进行编程。
此模式下的数据每TCK脉冲加载一位。
在尝试链路或器件操作之前，必须将Xilinx下载电缆从计算机连接到目标系统JTAG引脚，TDI，TCK，TMS和TDO。
Xilinx下载电缆电源引脚需要从电缆连接到电路板。
在iMPACT的图形视图中创建的边界扫描链必须与电路板上的链完全匹配。
这意味着如果链由8个设备组成，但只配置其中一个，则必须将所有8个设备添加到链中，其顺序与图形视图中板上的顺序完全相同。
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以下为原文

For general Boundary-Scan information, see the XAPP070 Application Note.
 
 
Boundary-Scan (JTAG) configuration mode enables you to perform Boundary-Scan-based configuration operations on any chain of JTAG compliant devices. The chain can consist of both Xilinx® and non-Xilinx devices, but only the BYPASS and HIGHZ operations are available for a non-Xilinx devices. 
Boundary-Scan is the most popular configuration mode due to its standardization and ability to program FPGAs, CPLDs, and PROMs through the same four JTAG pins. The data in this mode are loaded one bit per TCK pulse. 
Before a chain or device operation is attempted, a Xilinx download cable must be connected from the computer to the target system JTAG pins, TDI, TCK, TMS, and TDO. The Xilinx download cable power pins need to be connected from the cable to the board. The Boundary-Scan chain that is created in the graphical view in iMPACT must match the chain on the board, exactly. This means that if the chain consists of eight devices, but only one of them is going to be configured, all eight devices must be added to the chain in the exact same order as they occur on the board in the graphical view. 
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