[问答]

为什么XPA预测的功耗与实验室中观察到的实际功耗之间存在很大差距？

问答对人有帮助，内容完整，我也想知道答案 0 您好，我希望有人能够解释为什么XPA预测的功耗与实验室中观察到的实际功耗之间存在很大差距。我正在开发一种实现SHA-256的设计。由于SHA-256是一种散列算法，因此内部状态基本上是统计随机的，因此几乎所有触发器的活动率都以50％的切换率运行（每个位在统计上是随机的，所以有50％它与翻牌前一个状态相匹配的机会）。我正在为BRAMS和DSP48使用更加悲观的100％翻转率。没有I / O（通过BSCAN_SPARTAN6进行通信）。我正在使用“高效”分析。散热器设置为“自定义”，气流为250cfm，环境温度为45℃.XPA预测功耗为4.976W，其中42％来自逻辑，34％来自信号，9％来自时钟，7％来自PLL。然而，在实验室中，使用ztex FPGA模块1.15x（速度等级3，csg484封装），全铜散热器，导热油脂和安装在散热器上的风扇，17C环境温度，我观察到8.28W的功耗在DC / DC转换器的输入端。考虑到VCCINT引脚仍为6.21W（5.175A）的DC / DC转换器的最坏情况效率 - 比XPA预测的高25％。在实验室中，环境温度为17C，散热器为36C，PCB背面为42C（用IR温度计测量）。任何想法为什么XPA的预测与实际测量之间存在如此大的差距？这些工具的典型差距是25％吗？以上来自于谷歌翻译以下为原文 Hello, I was hoping somebody might be able to explain why there is a large gap between the power usage predicted by XPA and the actual power consumption observed in the lab. I'm working on a design that implements SHA-256. Since SHA-256 is a hashing algorithm, the internal state is basically statistically random, and as a result the activity rates for nearly all of the flops are operating at a 50% toggle rate (each bit is statistically random, so there's a 50% chance it matches the previous state of the flop). I'm using even more pessimistic 100% toggle rates for the BRAMS and DSP48s. There are no I/Os (communication is via BSCAN_SPARTAN6). I'm using "high effort" analysis. Heatsink is set to "custom" and airflow at 250cfm with ambient temperature of 45C. XPA predicts 4.976W of power consumption, with 42% of that coming from logic, 34% from signals, 9% from clocks, and 7% from PLLs. However, in the lab, using a ztex fpga module 1.15x (speed grade 3, csg484 package) with an all-copper heatsink, thermal grease, and a fan mounted on the heatsink, 17C ambient temperature, I observe 8.28W of power consumption at the input to the DC/DC converter. Factoring in the worst-case efficiency for the DC/DC converter that's still 6.21W (5.175A) at the VCCINT pins -- 25% higher than predicted by XPA. In the lab, ambient temperature is 17C, the heatsink is 36C and the back of the PCB is 42C (measured with an IR thermometer). Any ideas why there is such a large gap between XPA's predictions and the actual measurements? Is a gap of 25% typical for these tools? 0
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答案对人有帮助，有参考价值 0 eldentyrell写道：您好，我希望有人能够解释为什么XPA预测的功耗与实验室中观察到的实际功耗之间存在很大差距。我正在开发一种实现SHA-256的设计。由于SHA-256是一种散列算法，因此内部状态基本上是统计随机的，因此几乎所有触发器的活动率都以50％的切换率运行（每个位在统计上是随机的，所以有50％它与翻牌前一个状态相匹配的机会）。我正在为BRAMS和DSP48使用更加悲观的100％翻转率。没有I / O（通过BSCAN_SPARTAN6进行通信）。我正在使用“高效”分析。散热器设置为“自定义”，气流为250cfm，环境温度为45℃.XPA预测功耗为4.976W，其中42％来自逻辑，34％来自信号，9％来自时钟，7％来自PLL。然而，在实验室中，使用ztex fpga模块1.15x（速度等级3，csg484封装），全铜散热器，导热油脂和安装在散热器上的风扇，17C环境温度，我观察到8.28W的功耗在DC / DC转换器的输入端。考虑到VCCINT引脚仍为6.21W（5.175A）的DC / DC转换器的最坏情况效率 - 比XPA预测的高25％。在实验室中，环境温度为17C，散热器为36C，PCB背面为42C（用IR温度计测量）。任何想法为什么XPA的预测与实际测量之间存在如此大的差距？这些工具的典型差距是25％吗？显而易见的是：除了FPGA之外，DC / DC转换器的输出上还有什么？还应验证DC / DC转换器效率的假设。有没有办法测量转换器后的各个FPGA轨道消耗？ ----------------------------是的，我这样做是为了谋生。以上来自于谷歌翻译以下为原文 eldentyrell wrote: Hello, I was hoping somebody might be able to explain why there is a large gap between the power usage predicted by XPA and the actual power consumption observed in the lab. I'm working on a design that implements SHA-256. Since SHA-256 is a hashing algorithm, the internal state is basically statistically random, and as a result the activity rates for nearly all of the flops are operating at a 50% toggle rate (each bit is statistically random, so there's a 50% chance it matches the previous state of the flop). I'm using even more pessimistic 100% toggle rates for the BRAMS and DSP48s. There are no I/Os (communication is via BSCAN_SPARTAN6). I'm using "high effort" analysis. Heatsink is set to "custom" and airflow at 250cfm with ambient temperature of 45C. XPA predicts 4.976W of power consumption, with 42% of that coming from logic, 34% from signals, 9% from clocks, and 7% from PLLs. However, in the lab, using a ztex fpga module 1.15x (speed grade 3, csg484 package) with an all-copper heatsink, thermal grease, and a fan mounted on the heatsink, 17C ambient temperature, I observe 8.28W of power consumption at the input to the DC/DC converter. Factoring in the worst-case efficiency for the DC/DC converter that's still 6.21W (5.175A) at the VCCINT pins -- 25% higher than predicted by XPA. In the lab, ambient temperature is 17C, the heatsink is 36C and the back of the PCB is 42C (measured with an IR thermometer). Any ideas why there is such a large gap between XPA's predictions and the actual measurements? Is a gap of 25% typical for these tools? The obvious thing to check is: what else is hanging on the output of that DC/DC converter, other than the FPGA? Also assumptions of the DC/DC converter efficiency should be verified. is there any way to measure the individual FPGA rail consumption after the converter? ----------------------------Yes, I do this for a living.

2019-6-21 10:53:09 评论举报黄淳

答案对人有帮助，有参考价值 0 bassman59写道：显而易见的是：除了FPGA之外，DC / DC转换器的输出上还有什么？非常小。我能够通过JTAG停止DCM; 当我这样做时，整个电路板的功耗在DC / DC转换器输入时降至0.6W。 XPA声称我的设计的静态功耗为0.45W，因此只有0.15W的原因不明 - 远不及1.20W的差异。有没有办法测量转换器后的各个FPGA轨道消耗？可悲的是没有。以上来自于谷歌翻译以下为原文 bassman59 wrote: The obvious thing to check is: what else is hanging on the output of that DC/DC converter, other than the FPGA? Very litte. I am able to stop the DCMs via JTAG; when I do that, the power consumption from the entire board drops to 0.6W at the DC/DC converter input. XPA claims the static power consumption for my design is 0.45W, so there's only 0.15W unexplained -- nowhere near the size 1.20W discrepancy. is there any way to measure the individual FPGA rail consumption after the converter? Sadly there isn't.

2019-6-21 10:58:09 评论举报韩刚龙