双时钟速率SRAM设计

你好，
我有一个设计使用SRAM块，我想用一组输出寄存器配置它们。
这通常会在读取操作中引入额外的延迟周期。
但是，如果系统的其余部分以50MHz的频率运行，那么我可以将SRAMat设置为100MHz，从而保持20ns的SRAM读取时间（2 * 10ns），而不是系统逻辑的其余部分吗？
我的想法是，通过读操作，SRAM时钟（100MHz）的上升沿与系统时钟（50MHz）的上升沿一致将在总线上具有虚拟地址。
SRAM将在10ns后读取，10ns后SRAM内核输出寄存器也将被更新。
这在系统时钟的下一个上升沿（20ns之后）有效数据将在寄存器中可用。
如果这有效，那么我对以下进一步的问题表示感谢：
1.除了SRAM时钟（100MHz）上升沿与系统时钟（50 MHz）上升沿重合之外，还有SRAM时钟上升沿从系统时钟的角度来看是中间周期。
此时地址总线将没有有效数据。
因此，每隔一个SRAM时钟周期，SRAM内核和寄存器的输出都是无稽之谈。
由于无意义数据输出与系统时钟的上升沿不对应，因此这不会导致问题，但是您在此处看到了任何问题吗？
2.如何配置时序约束以忽略上述问题（即接受地址总线数据每10ns就不准备就绪，即使SRAM的时钟频率为100MHz也不需要这样做？）
3.有没有更好的方法来解决这个问题，假设我的目标是在没有50MHz系统的任何额外延迟的情况下实现_registered_ SRAM输出？
非常感谢任何帮助。



以下为原文

Hello,

I have a design that uses SRAM blocks and I would like to configure them with a single set of output registers.  This would ordinarily introduce an extra cycle of latency in a read operation.

However, would it be possible for me to clock the SRAM at 100MHz whilst the rest of the system is clocked at 50MHz, and thus maintain 20ns SRAM read time (2 * 10ns) from the prespective of the rest of the system logic?  My thinking is that with a read operation, rising edges on the SRAM clock (100MHz) that coincide with rising edges on the system clock (50MHz) will have a vaild address on the bus.  The SRAM will be read 10ns later and 10ns after that the SRAM core output registers will also have been updated.  This on the following rising edge of the system clock (20ns later) valid data will be available at the registers.

If this works, then I'd appreciate any comments on the following further issues:

1. In addition to the SRAM clock (100MHz) rising edges that coincide with the system clock (50 MHz) rising edges, there will also be SRAM clock rising edges that are mid-cycle from the perspective of the system clock.  At this time the address bus will not have valid data. Hence each other SRAM clock cycle, the output of the SRAM core and registers will be nonsense.  Since the nonsense data output does not correspond with a rising edge on the system clock this should not cause a problem, but are there any problems you see here?

2. How can I configure timing constraints to ignore the above issue (i.e. to accept that address bus data will not be ready each 10ns and not require this, even though the SRAM is clocked at 100MHz)?

3.  Is there a better way of approaching this, assuming my objective is to achive _registered_ SRAM output without any extra latency from the prespective of the 50MHz system?

Many thanks indeed for any help.