请问怎么在没有DCM PLL的情况下使用输入时钟信号？

尼科斯，
如果你需要在FPGA内部同步逻辑，最好进入BUFG资源，它也能够到达IO块（你不需要只使用BUFIO，你可以同样使用BUFG）。
如果您同时使用BUFIO和BUFG，那么当您不需要时，您将使用更多功率。
出于其他原因（功能），您可能需要BUFIO，这取决于您。
我假设你不需要在这里使用BUFIO。
1-13还意味着工具更容易满足时序要求，因为IOB DFF和逻辑都具有相同的相位（没有像1-12那样增加BUFG的延迟）。
这通常称为“系统同步”设计（所有信号都参考一个系统时钟）。
随着时钟速度的提高，人们通常会改为“源同步”设计，其中每组数据输入，数据输出都有自己的时钟（可能都是相同的时钟，但可能有不同的阶段来恢复数据）
可能在接收端）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Nikos,
 
If you need to synchronize logic inside the FPGA, it is best to get onto the BUFG resource, which is also able to get to IO blocks, too (you do not need to only use BUFIO, you may equally use a BUFG).
 
If you use both the BUFIO, and a BUFG, then you are using more power, when you do not need to.  You may need the BUFIO for other reasons (features) so that is up to you.  I am assuming you don't need to use the BUFIO here.
 
1-13 also means that it will be easier for the tools to meet timing, as the IOB DFF and the logic both have the same phase (no added delay of the BUFG as in 1-12).
 
This is commonly known as "system synchronous" design (all signals are referenced to one system clock).  As clock speeds get higher, people usually change to "source synchronous" design, where each set of data inputs, data outputs, have their own clocks (which may all be the same clock, but may have different phases to make recovery of the data possible at the receiving ends).
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢你们的快速回复。
也许这些事情对你来说很明显，但我还没有那么多使用FPGA的经验！
奥斯汀，
所以你实际上建议我在IBUFG之后我应该直接使用BUFG，然后计算我的所有逻辑。
老实说，我从为Spartan6设备编写的XILINX RTL中获取了BUFIO缓冲区的概念，用于千兆以太网的RX部分（这实际上也是我的应用程序）。
但内部逻辑由相同频率的内部时钟提供时钟。
因此，在这种情况下不需要BUFG缓冲区。
就个人而言，我还不熟悉可用的资源以及如何/何时使用它们。
然而，当我之前说过1-12中引入的相位差使得这个解决方案不可取时（至少对我来说）时，你对工具和时间的评论是我或多或少的想法。
关于“源同步”设计我现在还不太清楚为什么这种方法会对另一种方法有好处，但我会做我的研究以试图更好地理解这一点。
尼科斯



以下为原文

Thank you both for your fast replies. Perhaps these things are obvious for you, but I don't have yet so much experience in using FPGAs!
 
Austin,
So you're actually suggesting me that after the IBUFG I should use a BUFG directly and then clock all my logic. To be honest I took this idea of the BUFIO buffer from the XILINX RTL written for the Spartan6 device for the RX part of gigabit ethernet (this is actually my application too). But there the internal logic is clocked by internal clock of same frequency. So no BUFG buffer is needed in that case.
 
Personally I'm not yet so familiar with the available resources and how/when to use each one of them. However your comment about the tools and the timings is what I was more or less thinking when I said before that the phase difference introduced in 1-12 makes this solution not preferable (at least to me).
 
Regarding the "source synchronous" design I'm not quite sure right now why this approach would have benefits against the other one, but I'll do my research to try to understand this better.
 
Nikos

老实说，我从为Spartan6设备编写的XILINX RTL中获取了BUFIO缓冲区的概念，用于千兆以太网的RX部分（这实际上也是我的应用程序）。
用于GbE PHY的MII / RGMII接口使用125MHz时钟，完全在Spartan-6 BUFG缓冲区的功能范围内。
所以，是的，BUFG是IO逻辑和结构逻辑的时钟分配的正确选择。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

To be honest I took this idea of the BUFIO buffer from the XILINX RTL written for the Spartan6 device for the RX part of gigabit ethernet (this is actually my application too).
 
MII/RGMII interface used for GbE PHY uses a 125MHz clock, well within the capabilities of the Spartan-6 BUFG buffer.  So yes, BUFG is the correct choice for clock distribution to both IO logic and fabric logic.
 
-- Bob Elkind
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鲍勃，
谢谢你的回答。
最后一个澄清，以便我完全理解你在说什么！
使用IO逻辑，你的意思是输入触发器吗？
和结构逻辑所有其他逻辑？
我是否需要特别小心，以便将VHDL中描述的一些触发器映射到IO FF？
或者这是由工具自动完成的吗？
如果是这种情况，这种情况如何得到承认？
只需检测哪些触发器的输入连接到IO引脚？
再次感谢，
尼科斯



以下为原文

Bob,
 
thanks for your anwer. One last clarification, so that I understand completely what you're saying! With IO logic do you mean input flip-flops? And fabric logic all the other logic? And do I have to take some special care so that some of my flip-flops described in VHDL are mapped to IO FFs? Or is this automatically done by the tools? If that's the case, how is this situation recognized? Just by detecting which flip-flops have their inputs connected to IO pins?
 
thanks again,
Nikos

使用IO逻辑，你的意思是输入触发器吗？
并输出触发器。
IO逻辑当然不限于触发器（serdes，iodelay，iddr / oddr等）
和结构逻辑所有其他逻辑？
是的，除PLL / DCM等外
我是否需要特别小心，以便将VHDL中描述的一些触发器映射到IO FF？
您可以通过多种方式指导映射器。
XST流程属性（在ISE shell流程窗口中，选择Synthesize  -  XST流程，右键单击，选择“流程属性”，然后选择包I / O寄存器到IOB的选项）。
MAP流程属性（在ISE shell Process窗口中，选择MAP流程，右键单击，选择“流程属性”，然后 - 在Xilinx特定选项下 - 选择I / O寄存器/锁存到IOB的选项）。
.UCF / .NCF约束
Verilog / VHDL / Schematic约束
请参阅Constaints Guide UG625 IOB部分（在版本13.4中，这从第125页开始）。
或者这是由工具自动完成的吗？
如果启用此MAP或XST进程默认值，则为yes。
如果是这种情况，这种情况如何得到承认？
只需检测哪些触发器的输入连接到IO引脚？
对于输入FF，可能......输出FF不同。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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以下为原文

With IO logic do you mean input flip-flops?
 
And output flip-flops as well.   IO logic is not limited to flip-flops of course (serdes, iodelay, iddr/oddr, etc.)
 
And fabric logic all the other logic?
 
Yes, excepting PLL/DCMs, etc.
 
And do I have to take some special care so that some of my flip-flops described in VHDL are mapped to IO FFs?
 
You can direct the mapper in a number of ways.
 

• XST process property (in ISE shell Process window, select Synthesize - XST process, right-click, select "process properties", then select option for Pack I/O Registers into IOBs).
  

• MAP process property (in ISE shell Process window, select MAP process, right-click, select "process properties", then -- under Xilinx Specific Options -- select option for Pack I/O Registers/Latches into IOBs).
  

• .UCF / .NCF constraint
  

• Verilog/VHDL/Schematic constraint
  

 
See Constaints Guide UG625 IOB section (in version 13.4, this begins on page 125).
 
Or is this automatically done by the tools?
 
If you enable this MAP or XST process default, yes.
 
If that's the case, how is this situation recognized? Just by detecting which flip-flops have their inputs connected to IO pins?
 
For input FFs, probably...  Different for output FFs.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

nickagian写道：
谢谢你的回答。
最后一个澄清，以便我完全理解你在说什么！
使用IO逻辑，你的意思是输入触发器吗？
和结构逻辑所有其他逻辑？
我是否需要特别小心，以便将VHDL中描述的一些触发器映射到IO FF？
或者这是由工具自动完成的吗？
如果是这种情况，这种情况如何得到承认？
只需检测哪些触发器的输入连接到IO引脚？
如果您的时钟要求是您拥有的125 MHz时钟是设计中唯一需要的时钟，那么您根本不需要做任何特殊的事情。
不需要实例化缓冲区，当然也不需要DCM或PLL。
您需要做的就是编写描述逻辑的VHDL，确保它与125 MHz时钟同步。
这些工具将负责其余的工作。
任何可以在IOB中注册的输入或输出都将是，并且您的输入时钟将被放置在BUFG上，以便在整个芯片中正确分配。
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

nickagian wrote:
 
thanks for your anwer. One last clarification, so that I understand completely what you're saying! With IO logic do you mean input flip-flops? And fabric logic all the other logic? And do I have to take some special care so that some of my flip-flops described in VHDL are mapped to IO FFs? Or is this automatically done by the tools? If that's the case, how is this situation recognized? Just by detecting which flip-flops have their inputs connected to IO pins?
 

If your clocking requirement is such that the 125 MHz clock you have is the only one needed in the design, then you don't need to do anything special at all. No buffers need to be instantiated and certainly no DCM or PLL is required.
 
All you need to do is write VHDL describing the logic, making sure it's all synchronous to that 125 MHz clock. The tools will take care of the rest. Any inputs or outputs that can be registered in the IOB will be, and your input clock will be put on a BUFG for proper distribution throughout the chip.
 
-a
----------------------------Yes, I do this for a living.