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我对ISE 12.2有一些奇怪的问题。
(1)它似乎读取UCF文件,但所有输入节点都断开连接。 换句话说,在成功生成编程文件后,如果我打开Pinout Report文件,我会发现所有输入节点都未使用,尽管它们都在UCF文件中。 正如预期的那样,在通过Impact编程FPGA之后,输入引脚不响应输入信号。 输出节点在使用的引脚分布报告中可见。 但FPGA不起作用。 (2)如果我在ISE下打开PlanAhead I / O规划(预合成),我可以看到UCF文件中找到的所有节点和引脚。 但是我无法保存设计,因为菜单FILE> SAVE DESIGN显示为灰色。 我只能将文件导出到另一个PlanAhead文件夹,ISE似乎根本不读取此文件夹。 我曾在之前关于PlanAhead的帖子中寻求过帮助。 我怀疑一些项目设置 - 但不知道哪个。 请帮忙。 谢谢, 胜利者 以上来自于谷歌翻译 以下为原文 I am having strange problems with ISE 12.2. (1) It seems to read UCF files but all the input nodes are disconnected. In other words, after generating programming file successfully, if I open Pinout Report file, I find that all input nodes are unused though they are all there in the UCF file. As expected, the input pins do not respond to input signals after the FPGA has been programmed through Impact. The output nodes are seen in the Pinout Report as used. However FPGA does not work. (2) If I open PlanAhead I/O planning (pre-synthesis) under ISE, I can see all nodes and pins found in the UCF file. However I am unable to save the design as the menu FILE > SAVE DESIGN is greyed out. I can only export the files to another PlanAhead folder and ISE does not seem to read this folder at all. I have asked for help in a previous posting regarding PlanAhead. I suspect some project setting - but don't know which. Please Help. Thanks, Victor |
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嗨Victor,
在您进行更改之前,“保存”之前的计划是灰色的,这是正常的。 如果物理I / O显示正确的连接,那么你很高兴。 如果输入在设计之外进行了优化,则在实施期间输入可能会消失。 为了保持他们,他们必须推动输出! 我做了一个测试,以确保我在地图上收到一条消息,如“MAPLIB:连接到顶级端口CLKN的701信号已被删除”。 之后,在planahead中显示为连接的CLKN信号未显示在引脚输出报告中。 您可以考虑使用原理图查看器来确保按照您期望的方式合成设计。 (我以前在哪里听到过:笑笑:) -R -------------------------------------------------- --------------------------不要忘记回复,不要接受作为解决方案----------- -------------------------------------------------- --------------- 以上来自于谷歌翻译 以下为原文 Hi Victor, It is normal for the plan ahead "save" to be greyed out until you make a change. If the Physical I/O shows the right connections you're good to go. Inputs can go away during implementation if they are optimized out of the design. For them to be kept they must drive an output! I did a test of this to be sure and I get a message in map like " MAPLIB:701 signal connected to top level port CLKN has been removed." After that the CLKN signal which shows in planahead as connected does not show up in the pin out report. You could consider the schematic viewer to try to make sure the design is synthesized the way you expect. (Where have I heard this before:smileyhappy: ) -R ---------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution ---------------------------------------------------------------------------- |
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你好
我在查找Pad Report或Pinout Report时遇到问题。 我去Place& Rout Properties选择了Multip Pass Place& Route(根据帮助说明查找此报告), 仍然没有这个属性框中的选项。 请帮助我如何访问此Pad报告。 我正在使用ISE 11.1。 谢谢 杰米尔 以上来自于谷歌翻译 以下为原文 Hi I'm having problem with finding Pad Report or Pinout Report. I went to Place&Rout Properties to select Multip Pass Place&Route (as per Help instruction for find this Report), still there is no such an option in that Properties Box. Please help me how can I have access to this Pad Report. I'm using ISE 11.1. Thanks Cemil |
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杰米尔,
您需要查看“设计摘要”选项卡。 如果您已关闭此功能,则只需从项目 - >设计摘要/报告中重新启动它即可。 从那里我不相信pad默认打开,但是有一个pinout报告应该包含你要找的东西。 如果你想生成一个垫。 你可以点击框架左边的小图标,上面有一堆检查,然后启用打印垫报告生成。 希望这有帮助,乔恩 以上来自于谷歌翻译 以下为原文 Cemil, You'll want to look at the Design Summary Tab. If you've closed this, you can simply relaunch it from project-> design summary/reports. From there I dont believe pad is on by default, but there is a pinout report which should contain what you are looking for. If you want a pad generated. you can hit the little icon on the left of the frame that has a bunch of checks on it, and then enable pad report generation. Hope this helps, Jon |
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