UCF可以启用吗？

之前的问题是，如果你在UCF中定义了设计中根本不存在的东西，无论是PIN还是INST等，你都会在翻译过程中遇到错误。
我不知道10.1中对该功能的任何更改。



以下为原文

The problem before was that if you defined something in a UCF that did not exist in the design at all, whether it was a PIN or an INST, etc. you would get errors during translate.
 
I don't know about any changes to that functionality in 10.1.

你好吗？
是的，我同意你的看法。
我想我在ISE中看到了这个错误，但是当我使用命令行构建时我不再看到它。
不确定我是否遗漏了任何东西。



以下为原文

Hi morphiend,
 
Yes I agree with you that had been the issue. I think I had been seeing that error in ISE, but I no longer see it when I build using command line.
 
Not sure if I missed anything. 

也许您必须在命令行流中查看Translate报告（.bld文件）。



以下为原文

Perhaps you have to review the Translate report (.bld file) in the command line flow.

如果您只是想确认所有引脚都受到约束，请在地图报告（.mrp）或par报告（.par）中检查以下消息，具体取决于正在运行放置的应用程序。
信息：位置：834  - 仅锁定IO的子集。
在734个IO中，有562个被锁定 
和172没有锁定。
如果您想打印这些IO的名称， 
请将环境变量XIL_PAR_DESIGN_CHECK_VERBOSE设置为1。
您还可以检查par文件中的设计摘要： 
外部IOB数量389中的389 40％ 
在389 100％中定位的IOB数量389
关于不匹配的UCF引脚LOC约束，除非使用“-aul”开关，否则它们将导致ngdbuild中的错误。



以下为原文

If your are just trying to confirm that all of your pins are constrained, check for the following message in your map report (.mrp) or par report (.par) depending on which application is running placement.
 
INFO:Place:834 - Only a subset of IOs are locked. Out of 734 IOs, 562 are locked
   and 172 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
 
You can also check the design summary in the par file: 
   Number of External IOBs                 389 out of 960    40%
      Number of LOCed IOBs                 389 out of 389   100%
 Regarding unmatched UCF pin LOC constraints, they will cause errors in ngdbuild unless "-aul" switch is used.

嗨刚找到你的帖子，
我有一个问题。
是否有任何GUI等效于-aul。
这将非常方便。
我想只为Spartan 3AN入门套件提供一个ucf文件，而无需关心当前设计是否真正使用所有引脚。



以下为原文

Hi Just found your post,
 
I'm havig a question.
Is there any GUI equivalen to  the -aul.
This would come in quite handy.
I'd like to have only one ucf file for the Spartan 3AN starter kit without having to care whether the current design really uses all pins.
 
 

如果您只是想确认所有引脚都受到约束，请在地图报告（.mrp）或par报告（.par）中检查以下消息，具体取决于正在运行放置的应用程序。
信息：位置：834  - 仅锁定IO的子集。
在734个IO中，有562个被锁定 
和172没有锁定。
如果您想打印这些IO的名称， 
请将环境变量XIL_PAR_DESIGN_CHECK_VERBOSE设置为1。
您还可以检查par文件中的设计摘要： 
外部IOB数量389中的389 40％ 
在389 100％中定位的IOB数量389
您还可以将par生成的_pad.csv文件加载到ADEPT（http://mysite.verizon.net/jimwu88/adept/）。
它将在UCF中没有LOC的引脚上打印警告（参见下面的示例）：
警告：第23行：b放置在引脚P2上，但未定位在UCF中。警告：第24行：b放置在引脚P3上，但未定位在UCF中。警告：第25行：b放置在引脚P4上，
但未定位在UCF中。警告：第26行：q放在引脚P5上，但未定位在UCF中。
干杯，
吉姆
消息由jimwu在10-10-2009 11:19 AM编辑
干杯，吉姆



以下为原文

If your are just trying to confirm that all of your pins are constrained, check for the following message in your map report (.mrp) or par report (.par) depending on which application is running placement.
 
INFO:Place:834 - Only a subset of IOs are locked. Out of 734 IOs, 562 are locked
   and 172 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
 
You can also check the design summary in the par file: 
   Number of External IOBs                 389 out of 960    40%
      Number of LOCed IOBs                 389 out of 389   100%

You can also load the _pad.csv file generated by par into ADEPT (http://mysite.verizon.net/jimwu88/adept/). It will print out warnings on pins not LOC'ed in UCF (see example below):
 
WARNING:    line 23:b<5> is placed on pin P2, but is NOT LOCed in UCF.
WARNING:    line 24:b<6> is placed on pin P3, but is NOT LOCed in UCF.
WARNING:    line 25:b<7> is placed on pin P4, but is NOT LOCed in UCF.
WARNING:    line 26:q<0> is placed on pin P5, but is NOT LOCed in UCF.
 
Cheers,
Jim
Message Edited by jimwu on  10-10-2009 11:19 AMCheers,
Jim

klaus_f写道：我有一个问题。
是否有任何GUI等效于-aul。 
是的，它在“翻译”属性窗口中被称为“允许不匹配的LOC约束”。
干杯，
吉姆
干杯，吉姆



以下为原文

klaus_f wrote:

 I'm havig a question.
Is there any GUI equivalen to  the -aul.
 

Yes, it's called "Allow Unmatched LOC constraint" on the "Translate" properties window.
 
Cheers,
Jim
 
Cheers,
Jim

非常感谢这就是我想要的。
再见
ķ



以下为原文

Thanks A lot this is what I was looking for.
 
 
bye
 
K

你好，
我正在使用ISE 14.7并且也看到了相同的行为。
我特意在VHDL顶层添加了一个输入引脚，而没有在UCF中添加它，整个项目构建并生成aprogrammingfile而没有错误或警告！
即使选中“使用LOC约束”框并且未选中“允许不匹配的LOCConstraints”框也是如此。
查看引脚分布报告，ISE将未定义的输入分配给可用的引脚（在我的情况下为A12）。
我记得，如果在顶层定义的引脚与UCF不匹配，早期版本的ISE会给你一个错误。
在这种情况下，如何强制ISE发出错误？
问候
HV。



以下为原文

Hello,
 
I am using ISE 14.7  and are seeing the same behavior too.  I purposely added an input pin on the VHDL top level without adding it in the UCF and the whole project built and generated a programming file without errors or warnings!
Even with the "Use LOC Constraints" box checked and "Allow Unmatched LOC Constraints" box un-checked. 
Looking at the Pinout Report, ISE assigned the undefined input to an available pin (A12 in my case).
 
I recalled that earlier versions of ISE would give you an error if pins defined on top level does not match the UCF. 
How can I force ISE to give an error in this case?
 
Regards
HV.
 

你好HV，
你是部分正确的。
默认情况下，如果UCF中存在无法在设计中找到的约束，则ngdbuild会发出错误：
-aul（允许不匹配的LOC）
默认情况下，如果为pin，net或者指定了约束，程序将生成错误
在设计和NGD中找不到UCF或NCF文件中的实例名称
文件没有写。
使用此选项可为LOC生成警告而不是错误
约束并确保编写NGD文件。
（见UG628）
但是，如果存在无约束的I / O，则ngdbuild（也不是MAP）没有反对选项来发出错误。
最好的祝福
德赖斯
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以下为原文

Hi HV,
 
You are partially correct. By default, ngdbuild issues an error if there are constraints in the UCF that cannot be found in the design:
-aul (Allow Unmatched LOCs)By default the program generates an error if the constraints specified for pin, net, orinstance names in the UCF or NCF file cannot be found in the design, and an NGDfile is not written. Use this option to generate a warning instead of an error for LOCconstraints and make sure an NGD file is written. (see UG628)
 
However, there is no oppossite option for ngdbuild (nor for MAP) to issue an error if there are unconstrained I/Os.
 
 
Best regards
Dries
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这些工具（包括ISE和Vivado）现在需要对7系列设备的所有IO进行LOC约束。
此新限制不适用于旧架构。
我建议您检查报告以确认所有IO都是LOC'd。



以下为原文

The tools (both ISE and Vivado) now require LOC constraints on all IO for 7-Series devices. This new restriction does not apply to older architectures. I suggest that you check the reports to confirm that all IO is is LOC'd.

谢谢你们的回答。
我很高兴7系列设备在所有IO引脚上都需要LOC限制。
是否有计划更新ISE，以便将来在其他设备中包含此功能？
谢谢
HV。



以下为原文

Thanks you both for your answers.
 
Im glad that the 7-Series devices required LOC contraints on all IO pins.
Are there any plans on updating ISE to include this feature for other devices in the future?
 
Thanks
HV.
 
 

目前没有计划的ISE版本。



以下为原文

There are no future ISE releases planned at this time.