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这是安装: 1)用spartan-3a(1400,bga256准确)的板 2)配置模式引脚设置为SPI主设备(M [2:0] == 3'b001,VS [2:0] == 3'b111) 3)电路板上有一个空白的SPI闪存 这是案例: *配置失败后,FPGA继续将CS_B和MOSI驱动为低电平(未预期); * CCLK发布(预期); 我正在重新使用我板上现有连接器的一些引脚,所以我真的很缺少连接器上的引脚。 想法是仅使用4个spi引脚进行初始配置负载。 我期待FPGA在配置尝试失败后释放SPI接口,但事实并非如此。 PROG_B控制现在不是一个选项,因为它涉及更换电路板,我想避免。让我知道我的情况是否有一个“软”的解决方法。 问候, 弗拉德 以上来自于谷歌翻译 以下为原文 Hi! Here's the installation: 1) board with spartan-3a (1400, bga256 to be exact) 2) config mode pins set to SPI master (M[2:0] == 3'b001, VS[2:0] == 3'b111) 3) there's a blank SPI flash on the board Here's the case: * after failed configuration attempts FPGA continues to drive CS_B and MOSI low (not expected); * CCLK is released (expected); I'm re-using some pins of existing connector on my board so I am really really short of pins on that connector. The idea was to use just 4 spi pins for initial configuration load. I was expecting that FPGA will release SPI interface after failed config attempts, but it's not. PROG_B control is not an option now since it involves board change, which I would like to avoid. Let me know if there's a "soft" workaround for my case. Regards, Vlad |
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SPI连接器上有多少个GND引脚?
如果你有一个额外的GND引脚: 1.断开此引脚的GND 2.跳线PROG_B *到此引脚 当您将编程电缆(或任何配件连接到连接器)连接时,PROG_B *信号应为GND,迫使FPGA释放其SPI信号驱动器。 我不确定Spartan 3配置指南,UG332,但对于Spartan 6(配置用户指南),这个问题是如此清楚地描述,即使我不能错过它。 另一种方法是使用最小配置配置文件加载SPI存储器,使FPGA能够自配置,然后释放SPI接口,从而可以访问SPI总线。 另一种替代方案是通过JT***电缆)进行FPGA编程。 这使您可以在SPI存储器中加载“min config”配置文件。 (需要平台电缆加冲击SW或等效电路)。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 How many GND pins are on your SPI connector? If you have an extra GND pin: 1. disconnect GND from this pin 2. jumper PROG_B* to this pin When you connect your programming cable (or whatever mates to the connector), the PROG_B* signal should be GNDed, forcing the FPGA to release its drive of the SPI signals. I'm not sure about the Spartan 3 config guide, UG332, but for Spartan 6 (configuration user guide) this issue is so clearly described that even I couldn't miss it. An alternative is to load the SPI memory with a minimal configuration profile that will allow the FPGA to self-configure and then release the SPI interface, giving you access to the SPI bus. Another alternative is FPGA programming via JTAG (a la platform cable). This gives you access to loading the "min config" profile in the SPI memory. (requires Platform Cable plus Impact SW, or the equivalent). - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post |
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SPI连接器上有多少个GND引脚?
如果你有一个额外的GND引脚: 1.断开此引脚的GND 2.跳线PROG_B *到此引脚 当您将编程电缆(或任何配件连接到连接器)连接时,PROG_B *信号应为GND,迫使FPGA释放其SPI信号驱动器。 我不确定Spartan 3配置指南,UG332,但对于Spartan 6(配置用户指南),这个问题是如此清楚地描述,即使我不能错过它。 另一种方法是使用最小配置配置文件加载SPI存储器,使FPGA能够自配置,然后释放SPI接口,从而可以访问SPI总线。 另一种替代方案是通过JT***电缆)进行FPGA编程。 这使您可以在SPI存储器中加载“min config”配置文件。 (需要平台电缆加冲击SW或等效电路)。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 How many GND pins are on your SPI connector? If you have an extra GND pin: 1. disconnect GND from this pin 2. jumper PROG_B* to this pin When you connect your programming cable (or whatever mates to the connector), the PROG_B* signal should be GNDed, forcing the FPGA to release its drive of the SPI signals. I'm not sure about the Spartan 3 config guide, UG332, but for Spartan 6 (configuration user guide) this issue is so clearly described that even I couldn't miss it. An alternative is to load the SPI memory with a minimal configuration profile that will allow the FPGA to self-configure and then release the SPI interface, giving you access to the SPI bus. Another alternative is FPGA programming via JTAG (a la platform cable). This gives you access to loading the "min config" profile in the SPI memory. (requires Platform Cable plus Impact SW, or the equivalent). - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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谢谢,鲍勃!
你的建议很有价值。 由于我现有的主板没有选择进行PROG_B连接,因此我将退回使用JTAG(我正在使用它进行开发和测试)。 生产板(如果有的话)要么有一个板重新包含PROG_B连接,要么通过jtag使用最小配置加载器。 再次感谢,感谢您的反馈! 问候, 弗拉德 以上来自于谷歌翻译 以下为原文 Thanks, Bob! Your suggestions are valuable. Since my existing board have no options to make PROG_B connection I will fall-back to use JTAG (is what I am using now for development and testing). Production boards (if any) would either have a board respin to include PROG_B connection or use a min config loader through jtag. Thanks again, your feedback is appreciated! Regards, Vlad |
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如果安装FPGA配置,释放驱动SPI引脚的FPGA,则保持上拉或下拉Rs使能,使SPI线不浮空。
- 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 If you install an FPGA config which releases the FPGA driving the SPI pins, leave either pullup or pulldown Rs enabled, so that the SPI lines aren't floating. - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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