Spartan 6 PLL输出的同相匹配程度如何

ISE内部的时序分析工具使用时钟不确定性，我相信这是你想要的。
时钟不确定地处理静态相位偏移和输出时钟抖动。
因此，当您的时钟被分析时，这些因素将被用于实施。
我会说边缘将是“接近”，但这是主观的，所以最好检查工具的确切数字。
这回答了吗？



以下为原文

The timing analysis tools inside of ISE use clock uncertainty, which I beleive is what you're trying to get at.  The clock uncertaintly takes care of the static phase offset and the output clock jitter.  So when your clocks are analyzed, those factors will be taken into acocunt.  I would say the edges will be "close", but that's subjective, so best to check the tools for an exact number.
 
Does that answer it?

我的问题与时序分析和“时钟不确定性”关系不大。
我担心需要对从较慢时钟域到较快时钟域的信号进行特殊处理。
我并不担心绝对的“时钟不确定性”。
我担心同一PLL的两个输出之间的相位差。
如果可以说所有PLL输出都是由PLL内部的触发器驱动的 - 都具有相同的时钟 - 那么我会满意答案。
出于所有实际目的，这样的设计是'两个时钟上的死钟'对齐。
我认为你回答的问题和我想到的问题是相似的，但不完全一样。
在这种情况下，需要对时序分析器中的“竖起大拇指”或“大拇指向下” - 任何一个 - 进行质疑和假设，这将引导我们回到PLL输出 - 输出相位对齐的基本问题
。
这有意义吗？
- 鲍勃埃尔金德
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以下为原文

My question has very little to do with timing analysis and 'clock uncertainty'.  I'm concerned about the need for special handling of signals which cross from the slower clock domain to the faster clock domain.  I'm NOT worried about absolute 'clock uncertainty'.  I AM worried about phase difference between two outputs of the same PLL.
 
If it can be said that all PLL outputs are driven by flipflops internal to the PLL -- all with the same clock -- then I would be content with the answer.  Such a design is a 'both clocks dead nuts on' alignment, for all practical purposes.
 
I think the question you answered and the question I had in mind are similar, but not quite the same.  In this case, a 'thumbs up' or 'thumbs down' -- either one -- from the timing analyser need to be questioned for assumptions and methodology, and this would lead us back to the underlying question of PLL output-output phase alignment.
 
Does this make sense?
 
- Bob Elkind
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PLL的VCO是所有时钟输出的来源。
输出计数器（O [5：0]或CLKOUT {5：0]）实际上就是你所说的触发器。
对你而言，每个人的输出延迟可能略有不同。
那些不同的输出延迟是我们用静态相位偏移解决的问题。
为了更进一步，这些输出计数器还需要驱动时钟缓冲器，例如BUFH，BUFG等。当然，需要考虑由于不同缓冲器引起的路由差异。
由于它们是两个不同的时钟缓冲器，因此它们可能在物理上看到的路由噪声也有微妙的变化。
我希望这可以解决你的问题的主要来源，即所有时钟都来自同一个时钟源。
从那时起，一切都能够为该时钟添加额外的偏斜和/或抖动。



以下为原文

The PLL’s VCO is the source of all of the clock outputs. The output counters (O[5:0] or CLKOUT{5:0]) are effectively what you are calling flip flops. The kicker for you is that each may have slightly different output delays.  Those different output delays are what we're addressing with the static phase offset.
 
To take this one step further, those output counters additionally need to drive through clock buffers such as a BUFH, BUFG, etc. Of course routing differences due to different buffers will need to be taken into account. Since they’re two different clock buffers there’s also subtle variations in routing noise that they may physically see. 
 
I hope this addresses the main source of your question, though, that all of the clocks are derived off of the same clock source.  Everything from that point on has the ability to add additional skew and/or jitter to that clock.