GTP的Spartan 6 PCB设计问题

[问题1之后的短暂跟进问题]]
1.1） - >一般建议将MGT供应与其他供应分开吗？
或者可以 - 让我们说 - 从同一个电压调节器提供bank1，bank3，VCCINT以及（！）MGT。
（bank1和bank3相对占用I / O）
我无法在文档中找到一个非常明确的声明（ug386）。
（下一个帖子中的下一个（也是最后一个）问题）



以下为原文

[short follow-up question after question 1)]
 
1.1) -> Is it generally recommended to separate the MGT supply from the rest?
Or would it be okay to - let's say - supply the bank1, bank3, VCCINT as well as(!) the MGTs from the same voltage regulator.
(bank1 and bank3 are relatively occupied with used I/Os)
 
I wasn't able to find a very clear statement in the documentation (ug386).
 
(next (and last) question in the next posting)

正如我所说，我使用的是LX45T设备。
它有一个GTP银行（两个GTP DUAL）。
我需要4个接收器但没有发射器。
所以我使用两个DUAL（每个两个接收器），但两个都没有发射器。
因此，我的问题'2）'将是：
2.0）所有差分MGTTX数据引脚（MGTTXN0_101，...）都可以保持浮动，对吧？
2.1）我是否必须将MGTAVTTTX_101和MGTAVTTTX_123连接到1.2V或GND？
或者我必须让他们漂浮？
（我知道当整个（！）DUAL未被使用时该怎么办（如ug386 p166中所述）。但在这种情况下，使用两个DUAL的RX。）
2.2）我必须照常将MGTAVCCPLL0_101和MGTAVCCPLL0_123连接到1.2V，对吧？
我可以将MGTAVCCPLL1_101和MGTAVCCPLL1_123连接到GND吗？
我只需要一个外部时钟。
哦，我想我刚刚意识到，我也必须为这两个提供动力：参见ug386 p161表5-1
2.3。）根据'ug386 p44图2-5'我应该只能将一个外部差分refClk连接到MGTREFCLK0N_101和MGTREFCLK0P_101，并将这一个时钟馈送到两个DUAL？
你看到有什么问题吗？
2.4。）以下2.3。
其他三个差分REFCLK引脚对可以保持浮动状态，对吗？
（也在ug386 p44上）
这应该是安全的，因为我的refClkMUXes将不会选择它们，特别是因为浮动引脚后面没有IFBUSDS。
比安全更安全吗？
:)
非常感谢您的帮助。
最好的祝福，
肯
[编辑] uge  - > ug3，更正我的问题[/ edit]



以下为原文

As I said I am using an LX45T device. It has one GTP bank (two GTP DUALs).
 
I need 4 receivers but no transmitters.
So I am using both DUALs (two receivers each) but no transmitter in either of them.
 
 
Therefore my questions '2)' would be:
 
2.0) All the differential MGTTX data pins (MGTTXN0_101, ...) can stay floating, right?
 
2.1) Do I have to connect MGTAVTTTX_101 and MGTAVTTTX_123 to 1.2V or to GND? Or do I have to leave them floating?
(I know what to do when a whole(!) DUAL is unused (as described in ug386 p166). But in this case the RXs of both DUALs are used.)
 
2.2) I will have to connect MGTAVCCPLL0_101 and MGTAVCCPLL0_123 to 1.2V as usual, right?
Can I just tie MGTAVCCPLL1_101 and MGTAVCCPLL1_123 to GND? I just need one external clock.
Oh I think I just realized, that I will have to power these two as well: see ug386 p161 table 5-1
 
2.3.) According to 'ug386 p44 Figure2-5' I should be able to connect just one external differential refClk to MGTREFCLK0N_101 and MGTREFCLK0P_101 and feed that one clock to both DUALs? Do you see any problems?
 
2.4.) Following 2.3. the other three differential REFCLK pin pairs can remain floating, right? (also on ug386 p44)
That should be safe as my refClkMUXes will just not select them and especially because there will be no IFBUSDS behind the floating pins. Safer than safe? :)
 
Thank you very much for your help in advance.
 
Best regards,
Ken
 
 
[edit] uge -> ug3, correction to my questions [/edit]   

非常感谢您的快速回复！
让我写下更多信息：
董事会更像是一个研究原型。
提交后我只想订购一块PCB进行测试和设置。
后来，只有少数（（让我按字母顺序对它们进行编号，以便我们可以回到我最初的问题）：
答：您没有提到您正在使用哪个包（或者包装选择仍然流畅？）。
这可能有助于集中讨论。
我将使用XC6SLX45T-4FGG484C。
这不再是流动的，因为邻近的部门可以免费为我们提供工程样品。
（（...我知道......工程样品不是你想要的钱，我猜...但它们是免费的，我只需要几个））所以，除非我想出一个非常好的
切换的原因，我想坚持那个包。
但实际上我在这里发帖，因为我想了解这些问题。
B：知道你计划用于电路板叠加的电源平面层数也是有帮助的。
我计划使用6（或8）层，4（或6）个信号层。
因此，无论哪种方式，我只想使用一个GND层和一个VDD层。
这里有一个问题：这是不现实的/太多了吗？
指南文档xapp157.pdf尚未提及我的包。
C：这个设计对成本敏感吗？
或者你可以为防御设计多花一两块钱？
（例如额外的稳压器，额外的电路板层，更高的引脚数封装，将FPGA分成两部分等等）
相对。
额外的监管机构（或一般较小的部分）不应该是一个大问题。
我非常希望避免使用更大的FPGA（ - >最终更多的层）。
但是，如果这样可以节省我的时间，那么欢迎任何有关这方面的建议！
因为我的日程非常紧张。
我想尽快完成与FPGA相关的布局。
我将在下一篇文章中分享有关银行使用情况的一些细节。



以下为原文

Thank you very much for your quick reply!
Let me write down some more information then:
 
The board is more of a research prototype.
After submission I only want to order one PCB for testing and setup.
Later on, only a few (< 10) boards will be needed at the same time.
(This project is still very important to me, of course :D)
 
 
In regard to your questions (let me number them alphabetically, such that we can come back to my initial questions):
 
A: You don't mention which package you are using (or is the package   selection still fluid?).  This might help focus the discussion a bit.
I will be using a XC6SLX45T-4FGG484C. This is not really fluid anymore, because a neighboring department can provide us with engineering samples for free. (( ... I know... engineering samples are not what you want to bet your money on, I guess... but they are free and I need only a few)) So, unless I come up with a very good reason to switch, I would like to stick to that package. But actually I am posting here, because I want to find out about these issues.
 
 
B:  It would also be helpful to know how many power plane layers you are planning for your board stack-up.
I am planning to use 6 (or 8) layers with 4 (or 6) signal layers. So, either way I want to use only one GND layer and one VDD layer. A question here: Is this unrealistic / too much? The guideline documentation xapp157.pdf does not mention my package, yet.
 
 
C:  Is this design cost-sensitive?  Or can you spend an extra buck or  two for defensive design? (e.g. extra regulators, extra board layers,  higher pin-count package, splitting the FPGA into 2 parts, etc. etc.)
Relatively. Additional regulators (or smaller parts in general) shouldn't be a big problem.
I would very much like to avoid a bigger FPGA (-> eventually more layers). But any suggestions in that direction are welcome, if that saves me time in turn! Because my schedule is very tight. I would like to finish the FPGA-related layout ASAP.
 
 
I will share a few details on the bank usage in the next posting.

这有很多问题，你应该打开一个webcase。
Xilinx仍然在描述他们的生产硅 - 以及他们的生产*包装*。
您可能需要一些幕后信息，并且只能从Xilinx获取。
您可以从用户社区/论坛获得一些常规帮助，但我怀疑您需要得到Xilinx内部深层人员（或者在Xilinx内部了解合适人选的人）的指导。
如果你不赶时间，这将减少你成功的几率。
Xilinx仍然在表征，并且在专业人士理解之前在布局上滚动骰子，嗯......你得到了图片。
对不起，我无法提供更多帮助......
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

There are so many issues wrapped up with this, you should probably open up a webcase.  Xilinx is still characterising their production silicon -- and their production *packaging*.  There is probably some behind-the-scenes information which you need, and can only get from Xilinx.
 
You can get some general help from the user community/forum, but I suspect that you need to get guidance from someone deep(er) inside Xilinx - or someone who knows the right person inside Xilinx.
 
If you are un a hurry, this will cut down your odds of success.  Xilinx is still characterising, and rolling the dice on layout before the pros are settled on their understanding, well... you get the picture.
 
Sorry I couldn't be of more help...
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

无论如何，非常感谢你。
我会更多地考虑'MGT vs bank0'问题。
我可能会回过头来讨论它。
我很乐意让你（或其他人）加入=）
同时，你能不能快速地看看我在这个帖子中的＃3消息？
特别是2.0）和2.1）但其他人的快速评论也会很棒！
非常感谢提前！
PS：哦，请再次注意，我不会用MGT TX驱动任何信号。
所以也许（...）'bank0 3.3V'问题不是那么大，我可以冒险......？
编辑：“消息＃3”（是“＃4”......变老......）



以下为原文

Thank you very much anyway.
I will think about the 'MGT vs bank0' problem some more.
I might come back with an idea to discuss it a bit. I would be happy to have you (or others) join =)
 
Meanwhile, could you please take a quick last look at my message #3 in this thread?
 
Especially 2.0) and 2.1) but a quick comment on the rest would be great as well!
 
Big thanks in advance!
 
 
 
PS: Oh and please note again, that I will not be driving any signals with my MGT TXs. So maybe (...) the 'bank0 3.3V' issue is not that big and I can just risk it...?
 
 
 
 
 
edit: "message #3" (was "#4" ... getting old...)