如何生成具有不同相位的4个时钟信号？

lalobegar写道：
嗨，
我想生成具有不同相位（0,90,180,270）的4个时钟信号。
我知道这可以通过DCM完成，但我想将这些时钟信号用于FPGA内部的其他进程，有可能这样做吗？
问候。
你的问题毫无意义。
四个正交DCM输出应该在FPGA内部使用。
----------------------------是的，我这样做是为了谋生。



以下为原文

lalobegar wrote:
Hi,
 
I want to generate 4 clock signal with different phase (0,90,180,270). I know this can be done with a DCM, but I want to use those clock signals for other processes inside the FPGA, it is possible to do that?
 
Regards.

Your question make no sense. The four quadrature DCM outputs are supposed to be used inside the FPGA.
----------------------------Yes, I do this for a living.

好，谢谢！
现在我可以生成一个200MHz时钟的400MHz时钟，之后，我可以使用这个400MHz时钟作为另一个DCM的输入并产生前面提到的四个时钟信号吗？



以下为原文

Ok thanks! Now I can generate a 400MHz clock with a 200MHz clock, and after that, can I use this 400MHz clock as an input to another DCM and generate the four clock signals I mentioned before?

lalobegar写道：好的，谢谢！
现在我可以生成一个200MHz时钟的400MHz时钟，之后，我可以使用这个400MHz时钟作为另一个DCM的输入并产生前面提到的四个时钟信号吗？
首先，您不需要生成所有四个相位，因为您可以使用时钟的下降沿为触发器提供时钟，就像使用上升沿一样。
----------------------------是的，我这样做是为了谋生。



以下为原文

lalobegar wrote:
Ok thanks! Now I can generate a 400MHz clock with a 200MHz clock, and after that, can I use this 400MHz clock as an input to another DCM and generate the four clock signals I mentioned before?

First of all, you don't need to generate all four phases, because you can use the falling edge of a clock to clock a flip-flop just as well as using the rising edge.
----------------------------Yes, I do this for a living.

是的，你可以，但你应该将第一个的“锁定”信号分配给第二个的重置。
这意味着每当第一个dcm锁定时，第二个应该开始工作。
但你可以使用“两级级联”的ip核心代替。
它更简单，你不需要为它分配任何东西。
只有在第一页之后，它才会询问您将使用哪个时钟作为第二个DCM的输入，在这里您可以指定所需的时钟。
问候，
Ghasem



以下为原文

Yes, you can, but you should assign "locked" signal of the first one to the reset of the second one. It means that whenever the first dcm locked, the second should start working.
But you can use "two cascaded DCM" ip core instead. It's simpler and you don't need to assign anything to it. Only after the first page, it askes you which clock you are going to use as input to second DCM, and here you can specify the one you want.
Regards,
Ghasem

嗨，有没有办法生成clk系统的八个阶段。
阶段为（0,45,90,135,180,225,270,315）



以下为原文

Hi,

Is there a way for generate eight phases of the clk system. The phases being (0,45,90,135,180,225,270,315)

如何实例化两个级联DCM？
他们每个人独立还是有另一种方式？



以下为原文

How can I instantiate a two cascade DCM? Each of them independently or there is another way?

lalobegar写道：嗨，有没有办法生成clk系统的八个阶段。
阶段为（0,45,90,135,180,225,270,315）
你在做“在时钟的八个不同阶段采样输入信号”吗？
因为如果你是，你可能最好通过以适当的串行速率计时的1：8 ISERDES将该信号带入FPGA，然后寻找并行字中的转换。
----------------------------是的，我这样做是为了谋生。



以下为原文

lalobegar wrote:
Hi,

Is there a way for generate eight phases of the clk system. The phases being (0,45,90,135,180,225,270,315)

Are you doing the "sample an input signal on eight different phases of the clock" thing?
 
Because if you are, you might be better off bringing that signal into the FPGA via a 1:8 ISERDES clocked at an appropriate serial rate and then looking for the transition in the parallel word.
----------------------------Yes, I do this for a living.

是的我想要相同的输入信号，但有八个（或更多）不同的相位。
我猜你称之为“采样输入信号......”我可以用ISERDES做到这一点吗？
我也可以用PLL做，对吗？我可以将DCM的clk2x输出驱动到任何一个块（ISERDES或PLL）吗？



以下为原文

Yes I want the same input signal but with eight (or more) different phases. I guess you are calling this as "sample an input signal..."

So can I do this with ISERDES? Can I do it also with PLL, right?

Can I drive the clk2x output of the DCM to any of this blocks (ISERDES or PLL)?

lalobegar写道：是的我想要相同的输入信号，但有八个（或更多）不同的阶段。
我猜你称之为“采样输入信号......”我可以用ISERDES做到这一点吗？
我也可以用PLL做，对吗？我可以将DCM的clk2x输出驱动到任何一个块（ISERDES或PLL）吗？
你很困惑。
如果使用ISERDES概念，则不需要时钟的多个阶段。
你生成的时钟是你的时钟的4倍，那就是解串器时钟（DDR）。
因此，您希望将反序列化程序配置为1：8。
因此，对于并行（1X）时钟的每个刻度，您基本上可以获得所需的8个位。
这与使用DCM生成八个不同的时钟是完全不同的，这可能会导致您耗尽时钟资源并使定时成为一场噩梦。
您无法使用PLL生成多个阶段。
----------------------------是的，我这样做是为了谋生。



以下为原文

lalobegar wrote:
Yes I want the same input signal but with eight (or more) different phases. I guess you are calling this as "sample an input signal..."

So can I do this with ISERDES? Can I do it also with PLL, right?

Can I drive the clk2x output of the DCM to any of this blocks (ISERDES or PLL)?

You're confused.
 
If you use the ISERDES concept, you don't need the multiple phases of the clock. You generate a clock that's 4x your clock and that is the deserializer clock (at DDR). So you want to configure the deserializer to work as 1:8. So for each tick of the parallel (1X) clock you get 8 bits at essentially all of the phases you want.
 
This is entirely separate from generating eight different clocks with a DCM, which will likely cause you to run out of clocking resources and will make timing a nightmare.
 
You can't generate the multiple phases with a PLL.
----------------------------Yes, I do this for a living.