DMA缓冲区理解

你好。在从FIFO示例中，将DMACFG计数设置为2（从FIFO信道缓冲器计数2）。当数据从U转移到P时，数据在第一时间被写入第一缓冲器，并在第二时间写入第二缓冲器。之后，如果从奴隶FIFO（SLRD）读取不活跃，则缓冲器将是满的，并且不能写入更多的数据。一旦从奴隶FIFO开始读取，缓冲器将干净并准备好下一次传输。我的理解正确吗？
我还想用I2S传送短命令到FPGA，但是我找不到这样的固件例子。有人能给我一些建议吗？谢谢，乐华晨



     以下为原文
  Hello. In the Slave FIFO example, the dmaCfg.count is set to 2 (Slave FIFO channel buffer counts 2). When the data is transferred from U to P, the data is written to the first buffer at the first time and written to the second buffer at the second time. After that, if the Reading from Slave FIFO (SLRD) is not active, the buffer will be always full and no more data can be written. Once the Reading from Slave FIFO starts, the buffers will be clean and ready for the next transfer. Is my understanding right?
            
        I also want to use I2S to transfer short command to FPGA, but I can not find such firmware example. Could someone give me some suggestions?   
            
        Thanks,   
        Lehua Chen