使用2套Xilinx库的Modelsim怎么选择

你不能在同一次运行中使用两套库。
每次目标设备库发生更改时，您都需要单独运行。
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

you can't use two set of library in same run . You need to run separately each time when target device library got change.Thanks and Regards
Balkrishan
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我认为没有一个简单的解决方案，这在以前没有“多次”完成 - 这是一个相当新的问题。
Xilinx一直采用一套统一的仿真库。
过去，只有一套图书馆，它包括所有设备系列的电池;
同一个图书馆拥有多代设备的细胞;
你可以在同一组库中找到Spartan-3单元和Virtex-4和Virtex-5（...）。
这可能是因为单元格没有代代相传，或者它们会得到新名称（例如，我们有RAMB16.RAMB18，RAMB18E1 ......）。
如果一个单元具有相同的名称但行为略有不同，则它将使用SIM_DEVICE参数/ generic来确定它正在模拟的族。
所以这绝不是一个问题 - 如果你有一个Spartan-3和Virtex-5的设计，你只需要一套库，模拟器将拥有它所需要的一切。
然而，随着ISE / Vivado分裂，事情变得复杂。
ISE仍然拥有包含7个系列的所有内容的库。
Vivado只有7系列及更高版本（现在包括UltraScale和UltraScale +）
比如使用Spartan-6（用ISE实现）和Kintex-7（用Vivado实现）进行模拟，可以想到你可以简单地使用ISE库（因为它们包含7系列），但它实际上是
事实证明，ISE和Vivado中的7系列库略有不同。
Vivado库中的某些单元格具有ISE库中不存在的其他参数。
这些参数由Vivado（生成网表时）使用，但不由ISE使用。
这些必须手动解决。
但是对于V5和KintexUltrascale，你处于新的领域...... ISE库不包括UltraScale，而Vivado库不包括V5 ......
话虽这么说，我仍然认为细胞是独一无二的。
如果两个库中都存在具有相同名称的单元格，那么它应具有相同的功能，否则它将具有SIM_DEVICE参数（可能有一些新参数的警告，如上所述）。
我认为即使在V5和Kintex UltraScale之间仍然如此（它们从未共享过一个库）。
因此，您必须手动合并两个库 - 保留两个独特的单元格，保留两个库中相同的单元格的描述。
但是，您会发现一些不同的相同单元格的描述。
这些必须手动按摩。
您甚至可能需要进入V5网表描述并修改单元格的实例化（这很麻烦）。
所以（除非有人知道我不知道的事情），我认为没有一个干净的解决方案。
如果你能成功完成这项工作，请告诉我们......
Avrum



以下为原文

I don't think there is a simple solution to this, and this has not been done "many times" before - this is a fairly new problem.
 
Xilinx has always taken the approach of having one unified set of simulation libraries. In the past, there has only been one set of libraries, and it has included cells from all families of devices; the same library had the cells from many generations of devices; you would find Spartan-3 cells and Virtex-4 and Virtex-5 (...) all in the same set of libraries. This was possible either because cells didn't change functionality from generation to generation, or they would get new names (for example, we have RAMB16. RAMB18, RAMB18E1...). If a cell had the same name but slightly different behavior it would use the SIM_DEVICE parameter/generic to determine which family it was simulating. So this was never a problem - if you had a design with Spartan-3 and Virtex-5, you just needed the one set of libraries and the simulator would have everything it needed.
 
However, with the ISE/Vivado split, things have become complicated. ISE still has its libraries that has everything up to and including 7 series. Vivado has only the 7 series and beyond (which now includes UltraScale and UltraScale+)
 
For simulating, say, a design with Spartan-6 (implemented with ISE) and Kintex-7 (implemented with Vivado), one would have thought that you could simply use the ISE libraries (since they include the 7 series), but it actually turns out that the 7 series libraries in ISE and Vivado are slightly different. Some cells in the Vivado library have additional parameters that don't exist in the ISE libraries. These parameters are used by Vivado (when generating a netlist), but not by ISE. These had to be resolved manually.
 
But with V5 and KintexUltrascale, you are in new territory... The ISE libraries do not include UltraScale, and the Vivado libraries do not include V5...
 
That being said, I still think the cells are unique. If a cell with the same name exists in both libraries, then it should have the same functionality, or else it will have the SIM_DEVICE parameter (with the caveat of possibly having some new parameters, as I mentioned above). I think this is still true even between V5 and Kintex UltraScale (which have never shared a library together).
 
So you would have to manually merge the two libraries - keeping the unique cells from both, keeping either description for cells that are identical in both libraries. However, you will find some descriptions of the same cells that are different. These will have to be manually massaged. You might even need to go into your V5 netlist description and modify the instantiation of cells (which is messy).
 
So (unless someone knows something about this that I don't), I don't think there is a clean solution. Let us know if you manage to get this work...
 
Avrum

这里有一些想法：
比较可能并不那么容易：有些事情可能不会完全发生在锁定步骤中 - 可能会使眼球难以进行。
例如：PLL可能会在不同的时间锁定，某些IP接口可能会有稍微不同的延迟等等.BRAM可能或多或少相同，但DSP48已经改变了一点。
更复杂的核心现在可能有不同的接口。
可以在没有波形的情况下完成：如果你有自检的测试平台，那么两个设计的传递都是完成任务而不需要查看波形。
但是：前后都有一个舒适的因素。
要同时运行2个库，不应该通过操作库映射，配置等来实现吗？
也许有一个问题，但这里有一些猜测：
猜测＃1：逻辑上将库分开：1）“让modelsim使用2套原始库（即V5和Kintex）”：
- 假设该库名为“xilinx_lib”.-使V5库在逻辑上是唯一的：vmap ise_xilinx_lib ./ise/xilinx_lib 
vmap xilinx_lib ./vivado/xilinx_lib2）“告诉我的testbech中的每个实例使用哪个库”：
- 使用配置告诉v5设计使用逻辑库ise_xilinx_lib。
- 对于VHDL和Verilog，这可能略有不同
- 查看幻灯片9：http：//www.sutherland-hdl.com/papers/2000-HDLCon-presentation_Verilog-2000.pdf
- 或者，在VHDL设计中使用“ise_xilinx_lib”强制搜索和替换V5设计中对“xilinx_lib”的引用
猜＃2：使用系统verilog嵌套模块
1）“让modelsim使用2套原始库（即V5和Kintex）”：
2）“告诉我的testbech中的每个实例使用哪个库”：
- 使用System Verilog嵌套模块围绕V5设计包装模块。
这将在与kintex设计分开的命名空间内编译V5库。
模块v5_top; 
`include“ise / bufg.v” 
`include“ise / buf_io.v” 
... yada yada ... 
`include“my_design.v”
endmodule



以下为原文

 Here's a few thoughts:
 
Comparing may not be that easy: Some things might not happen exactly in lock step - could make eyeballing difficult.  Ex: PLLs might lock at different times, some IP interfaces might have slightly different latencies, etc..  BRAMs are probably more or less the same, but DSP48s have changed a bit.   More complicated cores might have different interfaces now.
 
Can do it without waveforms:  If you have self-checking testbenches, then a pass on both designs is mission accomplished without looking at waveforms.
 
However : There is a comfort factor is seeing before and after.   For running 2 libraries at the same time, shouldn't it be possible by manipulating library mappings, configurations and so on?   
 
Maybe there's a gotcha, but here's a few guesses:
 
guess #1:  Logically separate the libraries:
1) "Get modelsim to use 2 sets of primitive libraries (i.e. V5 and Kintex)" :
 - Say the library is called "xilinx_lib".
 - Make the V5 library logically unique :   vmap ise_xilinx_lib ./ise/xilinx_lib
                                                                 vmap  xilinx_lib    ./vivado/xilinx_lib
2) "Tell each instance in my testbech which library to use":
- Use a configuration to tell the v5 design to use the logical library ise_xilinx_lib.
- This might work for slightly differently for VHDL and Verilog
- Check out slide 9: http://www.sutherland-hdl.com/papers/2000-HDLCon-presentation_Verilog-2000.pdf
- OR, brute force search and replace references to "xilinx_lib" in the V5 design with "ise_xilinx_lib" in VHDL design
 
guess #2: Use system verilog nested modules
1) "Get modelsim to use 2 sets of primitive libraries (i.e. V5 and Kintex)" :
2) "Tell each instance in my testbech which library to use":
 - Wrap a module around the V5 design using System Verilog nested modules.  This compiles the V5 library inside a namespace separate from the kintex design.  
module v5_top;    `include "ise/bufg.v"    `include "ise/buf_io.v"    ... yada yada ...    `include "my_design.v"endmodule